Master’s in High-Speed Data Conversion
Online master's programme of 1,900 hours in high-speed data conversion — JESD204B/C and analogue front-ends. 12 modules covering sampling and quantisation, ADC and DAC architectures, sampling and comparator circuits, clocks and synchronisation, high-speed digital interfaces, board and front-end design, characterisation, digital calibration, software-defined radio and applications, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Understand the fundamentals of sampling and quantisation.
Analyse ADC and DAC architectures.
Design sampling, comparator and reference circuits.
Manage low-jitter clocks and synchronisation.
Implement high-speed digital interfaces.
Characterise converters according to IEEE standards.
Apply calibration and digital correction in real systems.
Who it's for
- Data converter design engineers.
- Mixed-signal engineers.
- High-speed hardware engineers.
- RF FPGA engineers.
- Characterisation engineers.
- Software-defined radio engineers.
- Engineering or science graduates looking to move into semiconductors.
What you'll work with
- IEEE 1241 (terminology and test methods for ADCs)
- IEEE 1658 (terminology and test methods for DACs)
- JESD204C (serial interface for data converters)
- IEEE 1057 (digitising waveform recorders)
- IPC-2141A (controlled impedance circuit boards)
- IEC 60748-4 (semiconductor devices — interface integrated circuits)
- Cadence Virtuoso
- MATLAB
- Keysight ADS
- AMD Vivado
- LTspice
12 modules
1.1Sampling theorem1.2Aliasing and undersampling1.3Quantisation and noise1.4Ideal signal-to-noise ratio1.5Effective number of bits (ENOB)1.6Spurious-free dynamic range1.7Clock jitter1.8Oversampling1.9High-speed applications1.10Case study: ADC requirements for a 5G receiver
2.1Flash ADC2.2Successive approximation ADC2.3Pipeline ADC2.4Sigma-delta ADC2.5Time-interleaved ADC2.6Ramp and folding ADCs2.7Speed-resolution comparison2.8Power consumption and figure of merit2.9State of the art2.10Lab: simulation of a SAR ADC
3.1R-2R ladder DAC3.2Current-steering DAC3.3Segmented DACs3.4Sigma-delta DAC3.5RF DACs3.6Sinc response and compensation3.7Glitches and their reduction3.8Static and dynamic linearity3.9DAC selection3.10Practical: measurement of a high-speed DAC
4.1Track and hold4.2Sampling switches4.3Bootstrapping4.4Dynamic comparators4.5Metastability4.6Residue amplifiers4.7Voltage references4.8Offset calibration4.9kT/C thermal noise4.10Lab: comparator design in Cadence
5.1Low-jitter clock generation5.2PLLs and synthesisers5.3Phase noise5.4Clock distribution5.5Multichannel synchronisation5.6JESD204B and JESD204C5.7SYSREF and deterministic latency5.8Jitter measurement5.9Impact on SNR5.10Practical: jitter budget for a system
6.1LVDS and CML6.2JESD204 interfaces6.3SerDes6.4Signal integrity6.5Equalisation6.6FPGA as receiver6.7Capture logic6.8Link testing6.9Error diagnosis6.10Lab: JESD204B link with an FPGA
7.1Analogue conditioning7.2ADC drivers7.3Baluns and transformers7.4Anti-aliasing filters7.5Mixed-signal layout7.6Ground and power planes7.7Decoupling7.8Isolation from digital noise7.9PCB simulation7.10Practical: layout of a 1 GSPS front-end
8.1IEEE 1241 and 1658 standards8.2Single-tone testing8.3Histogram and DNL/INL8.4Two-tone testing8.5Reference signal generators8.6Logic and spectrum analysers8.7Measurement automation8.8Measurement uncertainty8.9Characterisation reports8.10Lab: SFDR and ENOB characterisation
9.1Mismatch errors in interleaving9.2Foreground and background calibration9.3Gain and offset correction9.4Timing skew correction9.5Digital linearisation9.6DAC predistortion9.7Algorithms in FPGA9.8Power-accuracy trade-off9.9Calibration validation9.10Practical: time-interleaved mismatch correction
10.1Direct RF sampling10.2Digital up- and down-conversion10.3RFSoC architectures10.4FPGA processing10.5Multi-standard receivers10.6Digital radar10.7Test instrumentation10.8Satellite applications10.9Development platforms10.10Lab: direct-sampling receiver on an RFSoC
11.15G and 6G communications11.2Weather and air traffic radar11.3Medical imaging and ultrasound11.4Digital oscilloscopes11.5High-energy physics11.6Coherent optical communications11.7LiDAR11.8Radio astronomy11.9Requirements by application11.10Case study: converter selection for an ultrasound scanner
12.1System requirements12.2Architecture selection12.3Front-end design12.4Clock and synchronisation12.5Digital interface12.6Calibration12.7Characterisation12.8Analysis of results12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
100% online learning on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so you can combine it with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Cadence Virtuoso, MATLAB, Keysight ADS, AMD Vivado and LTspice, in free, academic or evaluation versions. Testing is studied through real procedures: dynamic characterisation with tones, jitter and phase noise measurements, and JESD204 link tests. Assessment is continuous by module, plus the final Master's Thesis.
Standards covered: IEEE 1241, IEEE 1658, JESD204C, IEEE 1057, IPC-2141A, IEC 60748-4.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Cadence Virtuoso, MATLAB, Keysight ADS, AMD Vivado and LTspice, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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