Diploma in HDL/HLS Design and Functional Verification
Online postgraduate diploma of 800 hours in HDL/HLS Design and Functional Verification: 8 modules covering RTL design in VHDL and SystemVerilog, digital microarchitecture, high-level synthesis, testbenches, UVM, coverage and formal verification, and FPGA prototyping, with an assigned technical tutor.
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Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Design synthesisable digital circuits in VHDL and SystemVerilog.
Define efficient microarchitectures with pipelining and safe clock domain crossing.
Generate hardware accelerators through high-level synthesis.
Build self-checking testbenches in SystemVerilog and cocotb.
Apply the UVM methodology in reusable verification environments.
Measure and close coverage using assertions and formal techniques.
Validate an IP block on FPGA with requirements traceability.
Who it's for
- Digital design engineers looking to strengthen their RTL and HLS skills.
- ASIC/FPGA verification engineers moving towards UVM and formal methods.
- FPGA hardware designers who need a rigorous verification workflow.
- HLS engineers turning C++ algorithms into hardware accelerators.
- Hardware validation engineers working with FPGA prototypes.
- Digital IP architects responsible for specification and sign-off.
- Engineering or science graduates looking to enter the semiconductor industry.
What you'll work with
- IEEE 1800-2017 (SystemVerilog hardware design and verification language)
- IEEE 1076-2019 (VHDL hardware description language)
- IEEE 1800.2-2020 (Universal Verification Methodology, UVM)
- IEEE 1364-2005 (Verilog hardware description language)
- IEEE 1850-2010 (Property Specification Language, PSL)
- RTCA DO-254 (design assurance for airborne electronic hardware)
- IEC 61508-2:2010 (functional safety requirements for E/E/PE hardware)
- AMD Vitis HLS and Vivado
- Siemens Questa
- Verilator
- cocotb
- Synopsys VCS
8 modules
1.1Abstraction levels and the digital design flow1.2Synthesisable combinational and sequential logic1.3Moore and Mealy state machines1.4Types, packages and parameterisation1.5Synchronous design and clock domains1.6Synchronous and asynchronous reset1.7Coding styles for synthesis1.8Inference of memories and DSP blocks1.9Lint and design rules1.10Lab: UART controller in SystemVerilog
2.1Datapath and control unit2.2Segmentation and pipelining2.3Interfaces with valid-ready handshake2.4Synchronous and asynchronous FIFOs2.5Clock domain crossing and synchronisers2.6Arbitration and resource multiplexing2.7Trade-offs between area, speed and power2.8Fixed-point arithmetic and saturation2.9Documentation of block specifications2.10Practical: pipelining an FIR filter
3.1From C++ algorithm to hardware3.2Pipeline, unroll and array_partition pragmas3.3Initiation interval and latency3.4AXI-Stream and AXI-Lite interfaces in HLS3.5ap_int and ap_fixed types3.6Dataflow and task-level parallelism3.7Report analysis and bottlenecks3.8C/RTL co-simulation3.9HLS compared with hand-written RTL3.10Lab: convolution accelerator with Vitis HLS
4.1Verification plan and requirements matrix4.2Design of self-checking testbenches4.3Stimuli and reference models4.4Directed versus random simulation4.5Classes, randomize and constraints in SystemVerilog4.6Python testbenches with cocotb4.7Simulation with Verilator and Questa4.8Waveform debugging4.9Automated regressions and scripts4.10Practical: cocotb testbench for a FIFO
5.1UVM architecture: agents, drivers and monitors5.2Sequences and sequencers5.3Scoreboards and predictor models5.4UVM phases and configuration database5.5Factory and component overrides5.6Register Abstraction Layer (RAL)5.7Reuse of verification components5.8Messaging and reporting in UVM5.9Integration into nightly regressions5.10Lab: UVM environment for an APB peripheral
6.1Code coverage: line, branch and toggle6.2Functional coverage with covergroups6.3Coverage closure and metrics6.4SVA assertions and temporal properties6.5Formal property verification6.6Equivalence checking between RTL and netlist6.7Structural CDC and RDC verification6.8Gap analysis and replanning6.9Verification closure sign-off6.10Workshop: SVA assertions for a bus protocol
7.1FPGA implementation flow7.2Clock and pin constraints7.3Integrated Logic Analysers (ILA)7.4Hardware-in-the-loop and co-simulation7.5Validation against the reference model7.6Version control and CI for HDL7.7DO-254 requirements for airborne hardware7.8Traceability between requirements and verification7.9Documentation for audit7.10Case study: validating an IP core on a Zynq board
8.1IP block specification8.2Implementation in RTL or HLS8.3Verification plan and environment8.4Functional coverage and assertions8.5Synthesis and resource analysis8.6FPGA prototype8.7Verification closure report8.8IP documentation8.9Report and presentation8.10Final project: final review with your tutor
How you'll learn
The programme is delivered 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so you can combine it with your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is AMD Vitis HLS and Vivado, Siemens Questa, Verilator, cocotb and Synopsys VCS, in free, academic or evaluation versions. Testing is studied through real procedures: simulation with self-checking testbenches, functional coverage closure and IP validation on FPGA. Assessment is continuous, module by module, plus the final project.
Standards covered: IEEE 1800-2017 (SystemVerilog), IEEE 1076-2019 (VHDL), IEEE 1800.2-2020 (UVM), IEEE 1364-2005 (Verilog), IEEE 1850-2010 (PSL), RTCA DO-254 and IEC 61508-2:2010.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- An internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with AMD Vitis HLS and Vivado, Siemens Questa, Verilator, cocotb and Synopsys VCS, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the programme software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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