Diploma in PDN, Decoupling and PI Simulation
Online postgraduate diploma of 800 hours in PDN design, decoupling and power integrity simulation. 8 modules covering PDN physics, decoupling capacitors, PCB stackup and planes, VRM interaction, DC IR-drop simulation, AC and transient simulation, and PDN measurement, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Calculate the target impedance of a rail from its load specifications.
Select and place decoupling capacitors taking ESL, ESR and DC bias into account.
Design PCB stackups that minimise the inductance of the distribution network.
Simulate DC IR drops and identify current hotspots.
Analyse the PDN impedance profile in the frequency domain and under transient conditions.
Measure the impedance of a PDN using the two-port shunt method.
Correlate simulated and measured results to validate a design.
Who it's for
- Power integrity engineers working on high-current, low-voltage rails.
- Digital hardware designers powering FPGAs, SoCs and DDR memory.
- PCB layout engineers responsible for stackup, planes and capacitor placement.
- Hardware validation engineers who measure rail impedance and ripple.
- SI/PI engineers looking to strengthen the power side of their work.
- High-speed board design leads who sign off on PDN performance.
- Engineering or science graduates seeking to enter consumer electronics.
What you'll work with
- IPC-2221B (generic standard on printed board design)
- IPC-2152 (current-carrying capacity in printed board design)
- IEEE 370-2020 (electrical characterisation of interconnects and fixtures)
- IPC-2141A (design guide for high-speed controlled impedance circuit boards)
- IPC-6012E (qualification and performance of rigid printed boards)
- IPC-4101 (base materials for rigid and multilayer printed boards)
- JEDEC JESD79-5 (DDR5 SDRAM standard)
- Ansys SIwave
- Cadence Sigrity PowerDC
- Keysight PathWave ADS
- Murata SimSurfing
- LTspice
8 modules
1.1Target impedance and ripple budget1.2Static IR drops and current density1.3Partial loop and via inductance1.4Transient response of digital loads1.5Plane resonances and cavity modes1.6Frequency-domain versus time-domain analysis1.7Current profiles of FPGAs and SoCs1.8Return paths and reference planes1.9Simultaneous switching noise (SSN)1.10Practical exercise: calculating the target impedance of an SoC
2.1ESR, ESL and effective capacitance model2.2Capacitance loss due to DC bias in MLCCs2.3C0G, X5R and X7R dielectrics compared2.4Anti-resonances between parallel capacitors2.5Value selection and logarithmic distribution2.6Low-ESL and interdigitated capacitors2.7Embedded capacitance and thin-dielectric planes2.8Polymer and tantalum bulk capacitors2.9Ageing and reliability of MLCCs2.10Lab: MLCC impedance measurement with a VNA
3.1Choosing a power-oriented stackup3.2Dielectric spacing and interplane capacitance3.3Plane splits and power islands3.4Power vias, antipads and the Swiss-cheese effect3.5Capacitor placement and pad fan-out3.6Via-in-pad and microvias in HDI3.7Copper thickness and current capacity3.8Noise coupling between adjacent rails3.9Interaction between power and signal integrity3.10Workshop: defining an eight-layer stackup
4.1VRM output impedance4.2Control loop bandwidth4.3Remote sensing and drop compensation4.4Stability with large capacitive loads4.5Switching ripple and output filtering4.6Ferrites and LC filters per rail4.7Sequencing and start-up ramps4.8VRM models for system simulation4.9Load-line and dynamic voltage tolerance4.10Case study: core rail of an FPGA
5.1Geometry extraction from the layout5.2Meshing and boundary conditions5.3Current density maps and hotspots5.4Maximum allowable current per via and trace5.5Steady-state electrothermal co-simulation5.6Sensitivity to copper thickness and temperature5.7Optimising the sense points5.8Maximum-drop compliance reports5.9Correlation with four-wire measurements5.10Lab: IR-drop analysis with PowerDC
6.1S-parameter extraction of the PDN6.2Impedance profile seen from the die6.3Package and chip power models (CPM)6.4Automatic optimisation of the capacitor bank6.5Transient simulation with real current profiles6.6Jitter induced by power supply noise6.7Noise coupled into sensitive analogue rails6.8Joint SI/PI simulation on DDR interfaces6.9Macromodelling and model order reduction6.10Practical exercise: impedance profile of a rail in SIwave
7.1Impedance measurement using the two-port shunt method7.2Low-noise, high-bandwidth probes7.3Ripple and transient measurement with an oscilloscope7.4Step injection with dynamic loads7.5Frequency response analysers7.6De-embedding fixtures and connectors7.7Correlation between simulation and measurement7.8Diagnosing resonances on a real board7.9Documenting validation results7.10Lab: two-port measurement of a 0.9 V rail
8.1Requirements for rails, loads and tolerances8.2Impedance budget per rail8.3Stackup proposal and decoupling strategy8.4DC simulation and drop verification8.5AC simulation and capacitor optimisation8.6Transient analysis of the most demanding scenario8.7Measurement plan and acceptance criteria8.8Conclusions and lessons learned8.9Report and presentation8.10Final project: final review with your tutor
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable materials, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, making it compatible with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Ansys SIwave, Cadence Sigrity PowerDC, Keysight PathWave ADS, Murata SimSurfing and LTspice, in free, academic or evaluation versions. Tests are studied on real procedures for rail impedance measurement with a VNA, IR-drop validation on high-density boards and simulation-measurement correlation of load transients. Assessment is continuous by module plus the final project.
Standards covered: IPC-2221B, IPC-2152, IEEE 370-2020, IPC-2141A, IPC-6012E, IPC-4101, JEDEC JESD79-5.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Ansys SIwave, Cadence Sigrity PowerDC, Keysight PathWave ADS, Murata SimSurfing and LTspice, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
Related programmes
Postgraduate Diploma in Multi-Constellation and SW Receivers
800-hour online Postgraduate Diploma in Multi-Constellation and SW Receivers. 8 modules covering IS-GPS-200, IS-GPS-705 and GNSS-SDR. Assigned tutor and enrolment open.
Postgraduate Diploma in MES/ERP/Historian Integration
Online 800-hour Postgraduate Diploma in MES/ERP/Historian integration. 8 modules covering IEC 62264, IEC 61512 and AVEVA PI System. Dedicated tutor and open enrolment.
Postgraduate Diploma in Field Testing and Interoperability
800-hour online Postgraduate Diploma in Field Testing and Interoperability. 8 modules covering ISO/IEC 9646-1, ETSI ES 201 873-1 (TTCN-3) and Keysight Nemo Outdoor. Dedicated tutor and…
More in Electronics, Embedded Systems & Telecom
All Electronics, Embedded Systems & Telecom programmes → · How to apply · Fees & financing · Scholarships