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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in Analogue and Mixed-Signal Design

Online master's programme of 1,900 hours in analogue and mixed-signal design (ADC/DAC, PLL, references, low-noise): 12 modules covering devices for analogue design, basic blocks, operational amplifiers, filters, data converters, integrated power management, mixed-signal circuits, analogue layout, verification, board-level design and chip manufacturing and testing, with an assigned technical tutor.

Duration1,900 hours · 12–14 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
Enrol now View syllabus Ask an advisor

Master’s in Analogue and Mixed-Signal Design — studying from New Zealand

Electronics and telecommunications are significant New Zealand industries, with Chorus operating the national fibre network and Spark, One NZ and 2degrees providing mobile services. Embedded systems and electronics design are strong in Auckland, Christchurch and Wellington, serving agricultural technology, medical devices and industrial automation. Engineers in this field work for telecommunications providers, electronics manufacturers and research groups, and the Radio Spectrum Management team within the Ministry of Business, Innovation and Employment oversees spectrum use.

Fees for New Zealand: NZ$11,700 (New Zealand dollar), with instalments and employer sponsorship available.

Relevant bodies in New Zealand

  • Institute of Electrical and Electronics Engineers (IEEE) New Zealand Section
  • Radio Spectrum Management (Ministry of Business, Innovation and Employment)
  • Telecommunications Carriers' Forum

Typical roles

  • Embedded Systems Engineer
  • Telecommunications Engineer
  • Electronics Design Engineer
  • Firmware Engineer

Questions from New Zealand

How do New Zealand bodies recognise electronics and telecom engineers?

Engineering New Zealand is the body for engineering registration, including Chartered Professional Engineer status. Telecommunications is overseen by the Commerce Commission and the Ministry of Business, Innovation and Employment, and radio spectrum is managed by MBIE. SEIUM's qualifications are private and not accredited by a national body, so employers decide their weight.

Which New Zealand employers hire embedded systems and telecom engineers?

Employers include telecommunications operators, electronics manufacturers, device makers, defence and aerospace suppliers, and research institutions. Hiring often prioritises practical embedded work, firmware projects and certifications relevant to the role. A private online qualification may help your application, but it does not guarantee an offer.

Is this manageable online from New Zealand, and what study load should I expect?

The programmes are online and in English, so no student visa is needed to study from New Zealand. Each has an assigned technical tutor and a final project. Specialist courses are 300 hours, postgraduate diplomas 800 and master's programmes 1,900. Fees can be paid in instalments, and employer sponsorship is possible, so check funding options first.

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Learning outcomes

What you will be able to do

01

Model devices for analogue design.

02

Design analogue blocks and operational amplifiers.

03

Design filters, oscillators and data converters.

04

Integrate power management and mixed-signal circuits.

05

Produce robust analogue layouts.

06

Verify designs against process variations.

07

Plan chip manufacturing and characterisation.

Profile

Who it's for

  • Analogue circuit designers.
  • Mixed-signal engineers.
  • Analogue layout engineers.
  • Analogue verification engineers.
  • Characterisation engineers.
  • Power management designers.
  • Engineering or science graduates seeking to enter the semiconductor industry.
Standards & tools

What you'll work with

  • AEC-Q100 (stress test qualification for automotive integrated circuits)
  • JEDEC JESD22-A114 (ESD sensitivity testing, human body model)
  • IEEE 1241 (terminology and test methods for ADCs)
  • IEEE 1076.1 (VHDL-AMS) (analogue and mixed-signal hardware description language)
  • IEC 60747-1 (semiconductor devices, general)
  • ISO 26262-11 (application of ISO 26262 to semiconductors)
  • Cadence Virtuoso
  • Spectre
  • LTspice
  • Siemens Calibre
  • KLayout
Syllabus

12 modules

  1. 1.1MOS transistor physics
  2. 1.2Large-signal models
  3. 1.3Small-signal models
  4. 1.4Weak inversion region
  5. 1.5Bipolar transistors
  6. 1.6Short-channel effects
  7. 1.7Thermal and flicker noise
  8. 1.8Process variability
  9. 1.9CMOS and BiCMOS technologies
  10. 1.10Case study: characterising a transistor in simulation
  1. 2.1Current sources and mirrors
  2. 2.2Single-stage amplifiers
  3. 2.3Cascode and folded cascode
  4. 2.4Differential pairs
  5. 2.5Active loads
  6. 2.6Bandgap voltage references
  7. 2.7Biasing
  8. 2.8Frequency response
  9. 2.9The gm/Id methodology
  10. 2.10Lab: designing a cascode mirror in Cadence
  1. 3.1Two-stage amplifier
  2. 3.2Miller compensation
  3. 3.3Stability and phase margin
  4. 3.4Fully differential amplifiers
  5. 3.5Common-mode feedback
  6. 3.6Slew rate and bandwidth
  7. 3.7Rail-to-rail
  8. 3.8Low-noise amplifiers
  9. 3.9Low-power amplifiers
  10. 3.10Practical exercise: designing a two-stage OTA
  1. 4.1Active RC filters
  2. 4.2gm-C filters
  3. 4.3Switched-capacitor filters
  4. 4.4Tuning and calibration
  5. 4.5Integrators
  6. 4.6RC and LC oscillators
  7. 4.7Comparators
  8. 4.8Sampling circuits
  9. 4.9Distortion and linearity
  10. 4.10Lab: switched-capacitor filter
  1. 5.1ADC and DAC specifications
  2. 5.2SAR ADCs
  3. 5.3Sigma-delta ADCs
  4. 5.4Pipeline ADCs
  5. 5.5Capacitive DACs
  6. 5.6Quantisation noise
  7. 5.7Calibration
  8. 5.8Performance measurements
  9. 5.9Architectures for sensors
  10. 5.10Practical exercise: 10-bit SAR ADC at block level
  1. 6.1Integrated LDO regulators
  2. 6.2Integrated DC-DC converters
  3. 6.3Charge pumps
  4. 6.4Precision references
  5. 6.5Reset and supervisors
  6. 6.6Battery management
  7. 6.7Energy harvesting
  8. 6.8Light-load efficiency
  9. 6.9Protections
  10. 6.10Lab: capacitor-less LDO
  1. 7.1PLLs and frequency synthesis
  2. 7.2DLLs
  3. 7.3Voltage-controlled oscillators
  4. 7.4Phase detectors
  5. 7.5Clock recovery
  6. 7.6Sensor interfaces
  7. 7.7Basic RF front-ends
  8. 7.8Analogue-digital integration
  9. 7.9Substrate noise
  10. 7.10Practical exercise: integer-N PLL in simulation
  1. 8.1Design rules
  2. 8.2Device matching
  3. 8.3Common centroid and interdigitation
  4. 8.4Guard rings
  5. 8.5Well proximity and stress effects
  6. 8.6Parasitics and extraction
  7. 8.7ESD protection
  8. 8.8Chip floorplanning
  9. 8.9DRC and LVS verification
  10. 8.10Lab: layout of a matched differential pair
  1. 9.1Corner simulation
  2. 9.2Monte Carlo
  3. 9.3Ageing analysis
  4. 9.4Post-layout simulation
  5. 9.5Mixed-signal verification
  6. 9.6Verilog-AMS behavioural models
  7. 9.7Functional safety verification
  8. 9.8Verification coverage
  9. 9.9Design reviews
  10. 9.10Practical exercise: Monte Carlo of a bandgap
  1. 10.1Selecting discrete amplifiers
  2. 10.2Sensor signal conditioning
  3. 10.3Instrumentation amplifiers
  4. 10.4Anti-aliasing filters
  5. 10.5External references and ADCs
  6. 10.6Mixed-signal PCB layout
  7. 10.7Grounding and shielding
  8. 10.8Board-level SPICE simulation
  9. 10.9Laboratory measurements
  10. 10.10Workshop: front-end for a strain gauge bridge
  1. 11.1Tape-out flow
  2. 11.2Multi-project wafers
  3. 11.3Packaging
  4. 11.4Production testing
  5. 11.5Laboratory characterisation
  6. 11.6Measurement benches
  7. 11.7Failure analysis
  8. 11.8Reliability and AEC-Q100 qualification
  9. 11.9Product documentation
  10. 11.10Case study: characterisation plan for a chip
  1. 12.1Block specification
  2. 12.2Architecture
  3. 12.3Transistor-level design
  4. 12.4Simulations
  5. 12.5Layout
  6. 12.6Extraction and post-layout
  7. 12.7Robustness verification
  8. 12.8Test plan
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

100% online programme on the SEIUM campus, with downloadable material, recorded lectures and an assigned technical tutor. No fixed timetables: you progress at your own pace within each intake, so it fits around your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is Cadence Virtuoso, Spectre, LTspice, Siemens Calibre and KLayout, in free, academic or evaluation versions. Testing is studied on real procedures: corner and Monte Carlo simulations, laboratory chip characterisation and noise and linearity measurements. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: AEC-Q100, JEDEC JESD22-A114, IEEE 1241, IEEE 1076.1 (VHDL-AMS), IEC 60747-1, ISO 26262-11.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of AEC-Q100, JEDEC JESD22-A114 and IEEE 1241 applied to real cases, not as a theoretical annex.
Industry software:Cadence Virtuoso, Spectre, LTspice, Siemens Calibre and KLayout, in free, academic or evaluation versions.
Master's Thesis with defence:A complete analogue block, from specification and transistor-level design to layout, post-layout extraction, robustness verification and test plan, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Block specification
Specify the analogue block and choose its architecture.
Transistor-level design
Size the circuit using the gm/Id methodology and simulate it.
Layout and extraction
Draw a matched layout, pass DRC/LVS and run post-layout simulation.
Robustness verification
Verify the design across corners and Monte Carlo and prepare the test plan.
Master's Thesis
A fully verified analogue block ready for tape-out, defended before a panel.
Career opportunities

Where this takes you

Analogue Circuit DesignerMixed-Signal EngineerAnalogue Layout EngineerAnalogue Verification EngineerCharacterisation EngineerPower Management Designer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

Apply now Scholarships
FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with Cadence Virtuoso, Spectre, LTspice, Siemens Calibre and KLayout, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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