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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in Precision Power Supply and Power Integrity

Online master's programme of 1,900 hours in precision power supply and power integrity (LDO/SMPS, ripple and layout). 12 modules covering power distribution architecture, precision linear regulators, point-of-load converters, PDN analysis and measurement, precision analogue supplies, high-performance digital systems, thermal design, layout, supervision and EMC, applied to IPC-2152, IPC-2221B and IEC 62368-1 with an assigned technical tutor.

Duration12–14 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
Enrol now View syllabus Ask an advisor

Master’s in Precision Power Supply and Power Integrity — studying from New Zealand

Electronics and telecommunications are significant New Zealand industries, with Chorus operating the national fibre network and Spark, One NZ and 2degrees providing mobile services. Embedded systems and electronics design are strong in Auckland, Christchurch and Wellington, serving agricultural technology, medical devices and industrial automation. Engineers in this field work for telecommunications providers, electronics manufacturers and research groups, and the Radio Spectrum Management team within the Ministry of Business, Innovation and Employment oversees spectrum use.

Fees for New Zealand: NZ$11,700 (New Zealand dollar), with instalments and employer sponsorship available.

Relevant bodies in New Zealand

  • Institute of Electrical and Electronics Engineers (IEEE) New Zealand Section
  • Radio Spectrum Management (Ministry of Business, Innovation and Employment)
  • Telecommunications Carriers' Forum

Typical roles

  • Embedded Systems Engineer
  • Telecommunications Engineer
  • Electronics Design Engineer
  • Firmware Engineer

Questions from New Zealand

How do New Zealand bodies recognise electronics and telecom engineers?

Engineering New Zealand is the body for engineering registration, including Chartered Professional Engineer status. Telecommunications is overseen by the Commerce Commission and the Ministry of Business, Innovation and Employment, and radio spectrum is managed by MBIE. SEIUM's qualifications are private and not accredited by a national body, so employers decide their weight.

Which New Zealand employers hire embedded systems and telecom engineers?

Employers include telecommunications operators, electronics manufacturers, device makers, defence and aerospace suppliers, and research institutions. Hiring often prioritises practical embedded work, firmware projects and certifications relevant to the role. A private online qualification may help your application, but it does not guarantee an offer.

Is this manageable online from New Zealand, and what study load should I expect?

The programmes are online and in English, so no student visa is needed to study from New Zealand. Each has an assigned technical tutor and a final project. Specialist courses are 300 hours, postgraduate diplomas 800 and master's programmes 1,900. Fees can be paid in instalments, and employer sponsorship is possible, so check funding options first.

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Learning outcomes

What you will be able to do

01

Design power architectures for electronic systems.

02

Select linear and switching regulators.

03

Analyse and optimise the power distribution network.

04

Measure power integrity accurately.

05

Power precision analogue circuits.

06

Design robust power layouts.

07

Implement supervision, protection and EMC compliance.

Profile

Who it's for

  • Power integrity engineers.
  • Power supply engineers working on point-of-load and precision rails.
  • Hardware designers responsible for board power architecture.
  • Power management applications engineers.
  • PCB engineers dealing with stack-up and decoupling.
  • Hardware validation engineers.
  • Engineering or science graduates looking to enter the semiconductor industry.
Standards & tools

What you'll work with

  • IPC-2152 (current-carrying capacity of printed board conductors)
  • IPC-2221B (generic standard on printed board design)
  • IEC 62368-1 (safety of audio/video, information and communication technology equipment)
  • CISPR 32 (electromagnetic emissions of multimedia equipment)
  • PMBus Specification 1.4 (digital power management bus)
  • AEC-Q100 (stress test qualification for automotive integrated circuits)
  • JEDEC JESD79-5 (DDR5 SDRAM standard)
  • Ansys SIwave
  • Cadence Sigrity
  • LTspice
  • Altium Designer
  • Keysight PathWave ADS
Syllabus

12 modules

  1. 1.1System power architecture
  2. 1.2Voltage rails and sequencing
  3. 1.3Voltage tolerances
  4. 1.4Dynamic processor loads
  5. 1.5Power integrity versus signal integrity
  6. 1.6Target impedance
  7. 1.7Supply noise and its effects
  8. 1.8Power budget
  9. 1.9Trends in core voltages
  10. 1.10Case study: power tree of an FPGA board
  1. 2.1LDO regulators
  2. 2.2Power supply ripple rejection (PSRR)
  3. 2.3Output noise
  4. 2.4Stability and ESR
  5. 2.5Voltage references
  6. 2.6Thermal drift
  7. 2.7LDOs for clocks and RF
  8. 2.8Heat dissipation
  9. 2.9Component selection
  10. 2.10Lab: PSRR measurement of an LDO
  1. 3.1Synchronous buck
  2. 3.2Multiphase regulators
  3. 3.3Voltage-mode and current-mode control
  4. 3.4COT control
  5. 3.5Transient response
  6. 3.6Switching ripple and noise
  7. 3.7Power modules
  8. 3.8PMBus and telemetry
  9. 3.9Light-load efficiency
  10. 3.10Practical exercise: design of a multiphase buck
  1. 4.1PDN model
  2. 4.2Power and ground planes
  3. 4.3Decoupling capacitors
  4. 4.4Resonances and anti-resonances
  5. 4.5Via and package inductance
  6. 4.6On-package capacitors
  7. 4.7Impedance versus frequency
  8. 4.8PDN simulation
  9. 4.9Decoupling optimisation
  10. 4.10Lab: PDN simulation with SIwave
  1. 5.1Ripple measurement
  2. 5.2Power rail probes
  3. 5.3Impedance measurement
  4. 5.4Two-port method
  5. 5.5Vector network analysers
  6. 5.6Transient load injection
  7. 5.7High-frequency noise measurement
  8. 5.8Measurement errors
  9. 5.9Measurement reports
  10. 5.10Practical exercise: PDN impedance measurement
  1. 6.1Powering ADCs and DACs
  2. 6.2Low-drift references
  3. 6.3Ground isolation
  4. 6.4Supply filters
  5. 6.51/f noise
  6. 6.6Powering sensors
  7. 6.7Powering amplifiers
  8. 6.8Design for metrology
  9. 6.9Laboratory power supplies
  10. 6.10Lab: powering a 24-bit ADC
  1. 7.1Processors and GPUs
  2. 7.2FPGAs and sequencing
  3. 7.3DDR memory
  4. 7.4Adaptive voltage scaling
  5. 7.5Real-time current measurement
  6. 7.6Dynamic power management
  7. 7.7Server power
  8. 7.848 V to point of load
  9. 7.9Load-step response
  10. 7.10Case study: powering a 300 A SoC
  1. 8.1Regulator losses
  2. 8.2PCB heat dissipation
  3. 8.3Thermal vias
  4. 8.4Component derating
  5. 8.5Capacitor ageing
  6. 8.6Electromigration
  7. 8.7MTBF reliability
  8. 8.8Thermal simulation
  9. 8.9Environmental testing
  10. 8.10Practical exercise: thermal analysis of a power stage
  1. 9.1Regulator placement
  2. 9.2Switching loops
  3. 9.3Current return
  4. 9.4PCB stack-up
  5. 9.5Trace and plane width
  6. 9.6Remote sense points
  7. 9.7Analogue–digital separation
  8. 9.8Design rules
  9. 9.9Layout review
  10. 9.10Workshop: power layout review
  1. 10.1Voltage supervisors
  2. 10.2Overcurrent protection
  3. 10.3Overvoltage protection
  4. 10.4Hot swap
  5. 10.5eFuses
  6. 10.6Sequencers
  7. 10.7PMBus telemetry
  8. 10.8Fault logging
  9. 10.9Functional safety
  10. 10.10Lab: configuring a PMBus sequencer
  1. 11.1Conducted noise from converters
  2. 11.2Input filtering
  3. 11.3Spread spectrum
  4. 11.4CISPR standards
  5. 11.5Transient immunity
  6. 11.6Electrical safety (IEC 62368)
  7. 11.7Energy efficiency
  8. 11.8Automotive requirements (AEC-Q)
  9. 11.9Documentation
  10. 11.10Case study: resolving noise in a power supply
  1. 12.1Power requirements
  2. 12.2Rail architecture
  3. 12.3Regulator design
  4. 12.4PDN design
  5. 12.5Simulation
  6. 12.6Layout
  7. 12.7Validation measurements
  8. 12.8Analysis of results
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so it fits around your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is Ansys SIwave, Cadence Sigrity, LTspice, Altium Designer and Keysight PathWave ADS, in free, academic or evaluation versions. Testing is studied through real procedures for PDN impedance measurement, ripple and transient measurement and thermal analysis with an infrared camera. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: IPC-2152, IPC-2221B, IEC 62368-1, CISPR 32, PMBus Specification 1.4, AEC-Q100, JEDEC JESD79-5.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of IPC-2152, IPC-2221B and IEC 62368-1 applied to real cases, not as a theoretical annex.
Industry software:Ansys SIwave, Cadence Sigrity, LTspice, Altium Designer and Keysight PathWave ADS, in free, academic or evaluation versions.
Master's Thesis with defence:Design of a complete power system, from rail architecture and regulators to PDN, layout and validation measurements, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

FPGA board power tree
Define the rail architecture, sequencing and power budget of an FPGA board.
Multiphase buck design
Design a multiphase point-of-load converter and check its transient response.
PDN simulation and measurement
Simulate the PDN in SIwave and measure its impedance against the target.
Layout review and EMC
Review the power layout and resolve a supply noise problem.
Master's Thesis
Design and validation of a complete power system, defended before a panel.
Career opportunities

Where this takes you

Power integrity engineerPower supply engineerHardware designerPower management applications engineerPCB engineerHardware validation engineer
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer able to run the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with Ansys SIwave, Cadence Sigrity, LTspice, Altium Designer and Keysight PathWave ADS, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software, and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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