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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in Real-Time Scheduling and Timing Analysis

Online master's programme of 1,900 hours in real-time scheduling and timing analysis (RMA/EDF, WCET, latencies): 12 modules covering fixed- and dynamic-priority scheduling, shared resources, WCET analysis, multicore platforms, RTOS, end-to-end analysis, mixed criticality and timing certification, with an assigned technical tutor.

Duration1,900 hours · 12–14 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Model real-time systems using task models.

02

Apply fixed- and dynamic-priority scheduling algorithms.

03

Manage shared resources without priority inversion.

04

Estimate worst-case execution time.

05

Analyse interference on multicore platforms.

06

Calculate end-to-end latencies.

07

Produce timing evidence for certification.

Profile

Who it's for

  • Real-time systems engineers.
  • Timing analysis engineers.
  • Safety-critical embedded software engineers.
  • Automotive software architects working with AUTOSAR.
  • Software certification engineers dealing with DO-178C or ISO 26262 timing evidence.
  • Researchers in real-time systems.
  • Engineering or science graduates seeking to enter aerospace.
Standards & tools

What you'll work with

  • ARINC 653 (avionics application partitioning interface)
  • RTCA DO-178C (software considerations in airborne systems)
  • EASA AMC 20-193 (use of multicore processors in avionics)
  • ISO 26262 (functional safety of road vehicles)
  • SAE AS5506 (AADL) (Architecture Analysis and Design Language)
  • IEEE 1003.1 (POSIX) (portable operating system interface)
  • AUTOSAR Classic Platform (automotive software architecture)
  • AbsInt aiT
  • Percepio Tracealyzer
  • FreeRTOS
  • MAST
  • Cheddar
Syllabus

12 modules

  1. 1.1Definition of a real-time system
  2. 1.2Hard, firm and soft deadlines
  3. 1.3Periodic, sporadic and aperiodic tasks
  4. 1.4Task model
  5. 1.5Processor utilisation
  6. 1.6Determinism and predictability
  7. 1.7Cyclic executives
  8. 1.8Reference critical systems
  9. 1.9Famous timing failures
  10. 1.10Case study: task model of a flight controller
  1. 2.1Rate Monotonic
  2. 2.2Deadline Monotonic
  3. 2.3Liu and Layland utilisation test
  4. 2.4Response time analysis
  5. 2.5Critical instant
  6. 2.6Tasks with arbitrary deadlines
  7. 2.7Release jitter
  8. 2.8Optimal priority assignment
  9. 2.9Implementation on an RTOS
  10. 2.10Lab: response time analysis
  1. 3.1Earliest Deadline First
  2. 3.2Least Laxity First
  3. 3.3Processor demand test
  4. 3.4Overload and degradation
  5. 3.5Aperiodic task servers
  6. 3.6Constant Bandwidth Server
  7. 3.7SCHED_DEADLINE in Linux
  8. 3.8Comparison with fixed priorities
  9. 3.9Use cases
  10. 3.10Practical exercise: EDF with SCHED_DEADLINE
  1. 4.1Priority inversion
  2. 4.2Priority inheritance
  3. 4.3Priority ceiling protocol
  4. 4.4Stack Resource Policy
  5. 4.5Blocking and its analysis
  6. 4.6Critical sections
  7. 4.7Interrupts and latency
  8. 4.8Lock-free design
  9. 4.9The Mars Pathfinder case
  10. 4.10Lab: priority inversion in FreeRTOS
  1. 5.1The WCET concept
  2. 5.2Static analysis
  3. 5.3Program flow analysis
  4. 5.4Cache and pipeline modelling
  5. 5.5aiT and OTAWA tools
  6. 5.6Measurement-based analysis
  7. 5.7Hybrid analysis
  8. 5.8Probabilistic WCET
  9. 5.9Design for analysability
  10. 5.10Practical exercise: measurement-based WCET estimation
  1. 6.1Interference on multicore
  2. 6.2Partitioned scheduling
  3. 6.3Global scheduling
  4. 6.4Task-to-core allocation
  5. 6.5Memory and bus contention
  6. 6.6Cache partitioning
  7. 6.7CAST-32A and AMC 20-193
  8. 6.8Hypervisors and isolation
  9. 6.9Interference analysis
  10. 6.10Lab: measuring interference on a multicore
  1. 7.1RTOS architecture
  2. 7.2Scheduler and context switching
  3. 7.3Timers
  4. 7.4Interrupt management
  5. 7.5FreeRTOS, Zephyr and VxWorks
  6. 7.6Linux PREEMPT_RT
  7. 7.7ARINC 653 partitioning
  8. 7.8AUTOSAR OS
  9. 7.9Latency measurement
  10. 7.10Practical exercise: interrupt latency measurement
  1. 8.1Cause-effect chains
  2. 8.2Data latencies
  3. 8.3Inter-task communication
  4. 8.4Holistic analysis
  5. 8.5CAN networks and response time
  6. 8.6Ethernet and TSN
  7. 8.7Compositional analysis
  8. 8.8Timing analysis tools
  9. 8.9System timing requirements
  10. 8.10Lab: end-to-end latency in an ECU
  1. 9.1Modelling with MARTE
  2. 9.2AADL and timing analysis
  3. 9.3SymTA/S and Chronos tools
  4. 9.4Timing in AUTOSAR
  5. 9.5Tracing with Tracealyzer
  6. 9.6Scheduling simulation
  7. 9.7Generating models from traces
  8. 9.8Integration into development
  9. 9.9Tool comparison
  10. 9.10Practical exercise: AADL model of an embedded system
  1. 10.1Vestal's model
  2. 10.2Mixed-criticality scheduling
  3. 10.3Temporal partitioning
  4. 10.4Guarantees per level
  5. 10.5Certification in mixed criticality
  6. 10.6Spatial and temporal isolation
  7. 10.7Certified hypervisors
  8. 10.8Cases in avionics and automotive
  9. 10.9Current research
  10. 10.10Workshop: designing a mixed-criticality platform
  1. 11.1Timing requirements in standards
  2. 11.2DO-178C and timing analysis
  3. 11.3ISO 26262 and timing
  4. 11.4Timing evidence
  5. 11.5Stress testing
  6. 11.6Runtime monitoring
  7. 11.7Overrun management
  8. 11.8Documentation
  9. 11.9Audits
  10. 11.10Case study: timing evidence for certification
  1. 12.1System and timing requirements
  2. 12.2Task model
  3. 12.3WCET estimation
  4. 12.4Schedulability analysis
  5. 12.5Implementation on an RTOS
  6. 12.6Measurements and traces
  7. 12.7End-to-end analysis
  8. 12.8Conclusions
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

100% online programme on the SEIUM campus, with downloadable material, recorded lectures and an assigned technical tutor. No fixed timetables: you progress at your own pace within each intake, so it fits around your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is AbsInt aiT, Percepio Tracealyzer, FreeRTOS, MAST and Cheddar, in free, academic or evaluation versions. Testing is studied on real procedures: schedulability analysis, latency measurement on hardware and timing stress campaigns. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: ARINC 653, RTCA DO-178C, EASA AMC 20-193, ISO 26262, SAE AS5506 (AADL), IEEE 1003.1 (POSIX), AUTOSAR Classic Platform.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of ARINC 653, RTCA DO-178C and EASA AMC 20-193 applied to real cases, not as a theoretical annex.
Industry software:AbsInt aiT, Percepio Tracealyzer, FreeRTOS, MAST and Cheddar, in free, academic or evaluation versions.
Master's Thesis with defence:A complete timing analysis of a real-time system, from task model and WCET estimation to schedulability and end-to-end latency analysis, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Task model
Define the system timing requirements and build its task model.
WCET estimation
Estimate worst-case execution times by static and measurement-based analysis.
Schedulability analysis
Apply response time analysis under fixed- and dynamic-priority scheduling.
RTOS implementation and tracing
Implement the tasks on an RTOS and validate them with measurements and traces.
Master's Thesis
End-to-end timing analysis with certification-ready evidence, defended before a panel.
Career opportunities

Where this takes you

Real-Time Systems EngineerTiming Analysis EngineerSafety-Critical Embedded Software EngineerAutomotive Software ArchitectSoftware Certification EngineerReal-Time Systems Researcher
Admissions & scholarships

Requirements

  • University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • Internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with AbsInt aiT, Percepio Tracealyzer, FreeRTOS, MAST and Cheddar, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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