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Master'sElectronics, Embedded Systems & Telecom Applications open

Master’s in Hypervisors and Mixed-Criticality

Online master's programme of 1,900 hours in hypervisors and mixed-criticality systems, covering partitioning, ARINC 653-like scheduling and safety islands. 12 modules covering hardware virtualisation, hypervisor types, spatial and temporal partitioning, guest operating systems, functional safety, cybersecurity, avionics and automotive applications, and verification, with an assigned technical tutor.

Duration1,900 hours · 12–14 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Understand the principles of mixed-criticality systems.

02

Make use of hardware virtualisation extensions.

03

Select and configure embedded hypervisors.

04

Implement spatial and temporal partitioning.

05

Mitigate interference on multicore platforms.

06

Apply functional safety requirements to partitioning.

07

Verify isolation and timing performance.

Profile

Who it's for

  • Embedded virtualisation engineers.
  • Mixed-criticality systems architects.
  • Avionics software engineers.
  • Functional safety engineers.
  • Hypervisor developers.
  • Real-time systems engineers.
  • Engineering or science graduates seeking to enter the aeronautical sector.
Standards & tools

What you'll work with

  • ARINC 653 (avionics application software standard interface for partitioning)
  • ISO 26262 (functional safety of road vehicles)
  • RTCA DO-178C (software considerations in airborne systems)
  • IEC 61508 (functional safety of electrical/electronic/programmable systems)
  • EASA AMC 20-193 (use of multicore processors in airborne systems)
  • RTCA DO-297 (integrated modular avionics development and certification)
  • ISO/SAE 21434 (road vehicle cybersecurity engineering)
  • CAST-32A (multicore processors position paper)
  • Xen
  • Jailhouse
  • Bao Hypervisor
  • QNX Hypervisor
  • seL4
Syllabus

12 modules

  1. 1.1The concept of mixed criticality
  2. 1.2Consolidation of functions
  3. 1.3Benefits and risks
  4. 1.4Criticality levels by sector
  5. 1.5Spatial and temporal isolation
  6. 1.6Federated versus integrated architectures
  7. 1.7Certification requirements
  8. 1.8Examples in avionics, automotive and industry
  9. 1.9Integration roadmap
  10. 1.10Case study: ECU consolidation in a vehicle
  1. 2.1ARM and x86 virtualisation extensions
  2. 2.2Exception levels in ARMv8
  3. 2.3Two-stage MMU
  4. 2.4IOMMU and SMMU
  5. 2.5Virtualised GIC interrupts
  6. 2.6Shared caches and interference
  7. 2.7Memory controllers
  8. 2.8Heterogeneous multicore processors
  9. 2.9TrustZone and secure environments
  10. 2.10Lab: exploring a multicore SoC
  1. 3.1Type 1 and type 2 hypervisors
  2. 3.2Microkernels and separation
  3. 3.3Static partitioning hypervisors
  4. 3.4Full virtualisation and paravirtualisation
  5. 3.5Examples: Xen, KVM, Jailhouse, Bao
  6. 3.6Certified commercial hypervisors
  7. 3.7Size of the trusted computing base
  8. 3.8Performance comparison
  9. 3.9Hypervisor selection
  10. 3.10Practical exercise: partitioning with Jailhouse
  1. 4.1Memory allocation to partitions
  2. 4.2Peripheral protection
  3. 4.3Device pass-through
  4. 4.4Peripheral virtualisation
  5. 4.5Inter-partition communication
  6. 4.6Secure shared memory
  7. 4.7Partition boot
  8. 4.8Partition fault management
  9. 4.9Verification of isolation
  10. 4.10Lab: inter-partition communication
  1. 5.1Partition scheduling
  2. 5.2ARINC 653 cyclic scheduling
  3. 5.3Hierarchical partition schedulers
  4. 5.4Interference on shared resources
  5. 5.5Cache colouring
  6. 5.6Memory bandwidth regulation
  7. 5.7WCET execution time analysis
  8. 5.8Interference measurement
  9. 5.9Temporal guarantees and their demonstration
  10. 5.10Practical exercise: cache colouring with Bao
  1. 6.1Real-time operating systems as guests
  2. 6.2Linux as a guest
  3. 6.3AUTOSAR in virtualisation
  4. 6.4Avionics operating systems
  5. 6.5Virtio paravirtualised drivers
  6. 6.6Guest power management
  7. 6.7Coordinated boot and shutdown
  8. 6.8Guest updates
  9. 6.9Guest debugging
  10. 6.10Lab: FreeRTOS and Linux on the same SoC
  1. 7.1IEC 61508 and partitioning
  2. 7.2ISO 26262 and freedom from interference
  3. 7.3DO-178C and DO-297
  4. 7.4Common cause analysis
  5. 7.5Safety arguments
  6. 7.6Hypervisor qualification
  7. 7.7Monitoring mechanisms
  8. 7.8Watchdogs and recovery
  9. 7.9Evidence for certification
  10. 7.10Workshop: freedom from interference analysis
  1. 8.1Hypervisor threat model
  2. 8.2Side-channel attacks
  3. 8.3Spectre and Meltdown
  4. 8.4Secure boot with a hypervisor
  5. 8.5Key management per partition
  6. 8.6Trusted execution environments
  7. 8.7Security audit
  8. 8.8ISO/SAE 21434 and virtualisation
  9. 8.9Common Criteria certified separation
  10. 8.10Practical exercise: cache side-channel analysis
  1. 9.1Integrated modular avionics (IMA)
  2. 9.2ARINC 653 in detail
  3. 9.3Multicore in avionics: CAST-32A
  4. 9.4EASA AMC 20-193 guidance for multicore
  5. 9.5Partitioning in flight systems
  6. 9.6Configuration tools
  7. 9.7Application integration
  8. 9.8Incremental certification of applications
  9. 9.9Aircraft case studies
  10. 9.10Case study: ARINC 653 configuration
  1. 10.1Central vehicle computers
  2. 10.2Virtualised digital cockpit
  3. 10.3Hypervisors in ADAS
  4. 10.4Virtualised industrial controllers
  5. 10.5Mixed-criticality robotics
  6. 10.6PLC virtualisation
  7. 10.7Partitioning in railway systems
  8. 10.8Virtualisation in medical devices
  9. 10.9Comparison of requirements by sector
  10. 10.10Lab: digital cockpit with a hypervisor
  1. 11.1Isolation testing
  2. 11.2Fault injection
  3. 11.3Interrupt latency measurement
  4. 11.4Hypervisor overhead measurement
  5. 11.5Stress testing
  6. 11.6Static analysis of the hypervisor
  7. 11.7Formal verification: seL4
  8. 11.8Tracing and analysis
  9. 11.9Verification reports
  10. 11.10Practical exercise: fault injection between partitions
  1. 12.1Definition of the mixed-criticality system
  2. 12.2Isolation requirements
  3. 12.3Hardware and hypervisor selection
  4. 12.4Partition design
  5. 12.5Platform configuration
  6. 12.6Guest integration
  7. 12.7Verification of isolation and timing
  8. 12.8Safety argument
  9. 12.9Master's Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

The programme is delivered 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so it can be combined with full-time work.

Each module combines theory, guided reading of the original standards and applied exercises. The working software is Xen, Jailhouse, Bao Hypervisor, QNX Hypervisor and seL4, in free, academic or evaluation versions. Practical work is based on real procedures for multicore interference measurement, fault injection testing and interrupt latency analysis. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: ARINC 653, ISO 26262, RTCA DO-178C, IEC 61508, EASA AMC 20-193, RTCA DO-297, ISO/SAE 21434, CAST-32A.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of ARINC 653, ISO 26262 and RTCA DO-178C applied to real cases, not as a theoretical annex.
Industry software:Xen, Jailhouse, Bao Hypervisor, QNX Hypervisor and seL4, in free, academic or evaluation versions.
Master's Thesis with defence:The design, configuration and verification of a mixed-criticality platform on an embedded hypervisor, with its safety argument, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

System and isolation requirements
Define the mixed-criticality system and its isolation requirements.
Hardware and hypervisor selection
Select the hardware platform and hypervisor and design the partitions.
Platform configuration
Configure the platform and integrate the guest operating systems.
Isolation and timing verification
Verify spatial isolation and timing behaviour and build the safety argument.
Master's Thesis
Present the platform design and verification results in a written thesis, defended before a panel.
Career opportunities

Where this takes you

Embedded virtualisation engineerMixed-criticality systems architectAvionics software engineerFunctional safety engineerHypervisor developerReal-time systems engineer
Admissions & scholarships

Requirements

  • A university degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • An internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with Xen, Jailhouse, Bao Hypervisor, QNX Hypervisor and seL4, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software, and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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