Master’s in Hypervisors and Mixed-Criticality Engineering
Online master's programme of 1,900 hours in hypervisor and mixed-criticality engineering. 12 modules covering embedded virtualisation, separation hypervisors, ARINC 653 partitioning, multicore interference, guest operating systems, fault management and certification of partitioned platforms under DO-297 and AMC 20-193, with an assigned technical tutor.
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What you will be able to do
Analyse the fundamentals of virtualisation in embedded systems.
Design mixed-criticality architectures with spatial and temporal isolation.
Configure separation hypervisors and ARINC 653-compliant partitions.
Manage interference in multicore processors.
Integrate operating systems of different criticality on a single platform.
Apply certification requirements to partitioned systems.
Evaluate the performance and determinism of virtualised platforms.
Who it's for
- Embedded virtualisation engineers working with Xen, Jailhouse or commercial hypervisors.
- Mixed-criticality systems architects.
- Avionics software engineers working on IMA platforms.
- Functional safety engineers assessing partitioned systems.
- Automotive platform engineers developing central vehicle computers.
- Systems integration engineers in aerospace, automotive or rail.
- Engineering or science graduates seeking to move into the aerospace sector.
What you'll work with
- ARINC 653 (avionics application software standard interface)
- RTCA DO-297 (integrated modular avionics development guidance)
- AMC 20-193 (use of multi-core processors)
- ISO 26262 (functional safety of road vehicles)
- IEC 61508 (functional safety of E/E/PE systems)
- RTCA DO-178C (software considerations in airborne systems)
- CAST-32A (multi-core processors)
- EN 50128 (software for railway control and protection systems)
- Xen Project
- Jailhouse
- PikeOS
- Wind River Helix Virtualization Platform
- QEMU
12 modules · 1900 h
1.1The trend towards function consolidation1.2The concept of mixed-criticality systems1.3DAL, ASIL and SIL levels1.4Spatial and temporal isolation between functions1.5Integrated modular avionics (IMA)1.6Zonal architectures in automotive1.7Advantages in weight, cost and power consumption1.8Technical risks of consolidation1.9Industry state of the art1.10Case study: consolidation of a vehicle's control units
2.1Type 1 and type 2 hypervisors2.2Full virtualisation and paravirtualisation2.3Virtualisation extensions in ARMv82.4Virtualisation extensions in x862.5Two-stage memory translation2.6Interrupt controller virtualisation2.7I/O virtualisation with SMMU2.8Static versus dynamic hypervisors2.9Comparison of embedded hypervisors2.10Practical: ARM virtual machines on QEMU
3.1The separation kernel concept3.2Static resource partitioning3.3Jailhouse architecture3.4Xen architecture in embedded systems3.5Commercial certifiable hypervisors3.6Microkernels and their relationship with hypervisors3.7Direct device assignment3.8Inter-partition communication3.9Cell configuration and boot3.10Lab: isolated cells with Jailhouse
4.1The ARINC 653 partition model4.2Major and minor frame scheduling4.3Sampling and queuing ports4.4Health monitoring4.5APEX services for applications4.6Configuration through XML files4.7Parts 1, 2 and 4 of the standard4.8Commercial implementations of the standard4.9DO-297 requirements for IMA4.10Workshop: partition scheduling table
5.1Hierarchical partition scheduling5.2Virtual machine schedulers5.3Compositional schedulability analysis5.4Latency of virtualised interrupts5.5Real-time scheduling in Xen5.6CPU bandwidth reservation5.7Impact of context switches5.8Measuring jitter in partitions5.9Optimising temporal determinism5.10Practical: latency measurement in a partition
6.1Sources of inter-core interference6.2Shared cache contention6.3Memory and DDR controller contention6.4Cache partitioning by page colouring6.5Memory bandwidth regulation6.6Interference on buses and interconnects6.7CAST-32A and AMC 20-193 requirements6.8Measuring interference with microbenchmarks6.9Hardware performance counters6.10Lab: cache colouring in a hypervisor
7.1Linux as a guest system7.2Guest RTOSs in critical partitions7.3Certified operating systems as guests7.4VirtIO paravirtualised drivers7.5Coordinated guest boot7.6Sharing I/O devices7.7Shared graphics and displays7.8Inter-guest communication through shared memory7.9Power management across partitions7.10Case study: Linux and an RTOS on the same platform
8.1Fault containment between partitions8.2Health status monitoring8.3Isolated partition restart8.4Partition and system watchdogs8.5Redundancy within a platform8.6ECC memory error handling8.7Degraded operating modes8.8Common-cause failure analysis8.9Fault-injection testing8.10Workshop: health management strategy for a platform
9.1IMA platform and incremental certification9.2Role of the platform supplier9.3Evidence of robust isolation9.4ISO 26262 requirements for hypervisors9.5Safety elements out of context (SEooC)9.6Configuration qualification9.7Partitioning verification testing9.8Documentation for the authority9.9Reuse of evidence9.10Case study: certification package for a hypervisor
10.1Vehicle central computers10.2Integration of AUTOSAR Classic and Adaptive10.3Mixed-criticality digital cockpit10.4Hypervisors in railway systems10.5EN 50128 and EN 50657 requirements10.6Platforms for industrial robotics10.7Medical equipment with consolidated functions10.8Containers versus hypervisors10.9Trends in software-defined vehicles10.10Practical: architecture of a central computer
11.1Virtualisation overhead metrics11.2End-to-end latency and jitter11.3Real-time benchmarks11.4Virtualised I/O performance11.5Hypervisor tracing11.6Interference profiling11.7Configuration tuning11.8Comparison between hypervisors11.9Platform characterisation report11.10Lab: timing characterisation of a hypervisor
12.1Definition of the consolidation case12.2Analysis of criticality requirements12.3Design of the partitioned architecture12.4Hypervisor configuration12.5Interference analysis12.6Isolation verification12.7Certification plan12.8Conclusions and future work12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so it fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Xen Project, Jailhouse, PikeOS, Wind River Helix Virtualization Platform and QEMU, in free, academic or evaluation versions. Work is based on real procedures: configuring partitions in a separation hypervisor, analysing interference in multicore processors and consolidating functions of different criticality on one platform. Assessment is continuous per module, plus the final Master's Thesis.
Standards covered: ARINC 653, RTCA DO-297, AMC 20-193, ISO 26262, IEC 61508, RTCA DO-178C, CAST-32A, EN 50128.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Xen Project, Jailhouse, PikeOS, Wind River Helix Virtualization Platform and QEMU, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software, and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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