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Master'sAutonomous, ADAS & Software-Defined Vehicle Applications open

Master’s in Heterogeneous Computing Engineering for AD — CPU/GPU/NPUs, Scheduling, Thermal/Power Budgeting

Online master's programme of 1,900 hours in heterogeneous computing engineering for autonomous driving, structured in 12 modules covering CPU/GPU/NPU architectures, automotive SoCs, parallel programming, neural network inference, real-time scheduling, thermal and power budgeting and hardware functional safety under ISO 26262 and AEC-Q100, with an assigned technical tutor.

Duration1900 h
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Analyse the computing requirements of an autonomous driving stack.

02

Compare heterogeneous architectures and automotive SoCs.

03

Programme accelerators using CUDA and parallel frameworks.

04

Optimise neural network inference.

05

Schedule tasks with real-time requirements.

06

Manage thermal and power budgets.

07

Develop a complete heterogeneous computing project for autonomous driving.

Profile

Who it's for

  • Computing platform engineers selecting and integrating SoCs for autonomous driving.
  • Inference optimisation engineers deploying neural networks on embedded accelerators.
  • Automotive hardware architects defining central compute units.
  • Embedded systems engineers working with GPUs, NPUs and DSPs.
  • Performance engineers focused on latency, throughput and efficiency.
  • Hardware functional safety engineers working with ISO 26262 metrics.
  • Engineering or science graduates aiming to enter the automotive sector.
Standards & tools

What you'll work with

  • ISO 26262 (functional safety of road vehicles)
  • AEC-Q100 (stress qualification of automotive integrated circuits)
  • ISO 21448 (safety of the intended functionality, SOTIF)
  • ISO/SAE 21434 (road vehicle cybersecurity engineering)
  • IEC 61508 (functional safety of E/E/PE systems)
  • JEDEC JESD51 (thermal measurement of semiconductor packages)
  • ISO 16750-4 (climatic loads for automotive electrical equipment)
  • MISRA C++:2023 (coding guidelines for safety-critical C++)
  • CUDA
  • NVIDIA TensorRT
  • Apache TVM
  • ANSYS Icepak
  • Nsight Systems
Syllabus

12 modules · 1900 h

  1. 1.1Computing requirements of the AD stack
  2. 1.2Perception, prediction and planning workloads
  3. 1.3Operations per second and TOPS
  4. 1.4End-to-end latency
  5. 1.5System energy consumption
  6. 1.6Evolution of computing platforms
  7. 1.7Centralised computing architectures
  8. 1.8Hardware cost
  9. 1.9Silicon trends
  10. 1.10Case study: computing budget of a robotaxi
  1. 2.1Multi-core ARM and x86 CPUs
  2. 2.2GPUs for inference
  3. 2.3NPUs and dedicated accelerators
  4. 2.4DSPs and vision accelerators
  5. 2.5FPGAs in automotive
  6. 2.6Lockstep safety islands
  7. 2.7Memory hierarchy
  8. 2.8On-chip interconnect
  9. 2.9Cache coherence
  10. 2.10Lab: profiling on a heterogeneous SoC
  1. 3.1NVIDIA DRIVE Orin and Thor
  2. 3.2Qualcomm Snapdragon Ride
  3. 3.3The Mobileye EyeQ family
  4. 3.4Texas Instruments TDA4
  5. 3.5The Renesas R-Car family
  6. 3.6Performance comparison
  7. 3.7Software and SDKs
  8. 3.8AEC-Q100 component qualification
  9. 3.9Manufacturers' roadmaps
  10. 3.10Practical exercise: SoC comparison by use case
  1. 4.1The CUDA programming model
  2. 4.2OpenCL and SYCL
  3. 4.3Data and task parallelism
  4. 4.4Kernel optimisation
  5. 4.5Shared and global memory
  6. 4.6Host-device transfers
  7. 4.7DSP programming
  8. 4.8Optimised libraries cuBLAS and cuDNN
  9. 4.9Debugging parallel code
  10. 4.10Workshop: CUDA pre-processing kernel
  1. 5.1Model compilation
  2. 5.2TensorRT and optimisations
  3. 5.3INT8 and FP8 quantisation
  4. 5.4Pruning and distillation
  5. 5.5Layer fusion
  6. 5.6Partitioning across accelerators
  7. 5.7Batch size and latency
  8. 5.8Model compilers such as TVM
  9. 5.9Accuracy validation
  10. 5.10Lab: deployment with TensorRT
  1. 6.1Task scheduling in heterogeneous systems
  2. 6.2DAG task graphs
  3. 6.3Priorities and preemption
  4. 6.4GPU scheduling
  5. 6.5Response-time analysis
  6. 6.6WCET on heterogeneous hardware
  7. 6.7Memory interference
  8. 6.8Temporal partitioning of resources
  9. 6.9Analysis tools
  10. 6.10Practical exercise: analysis of a processing chain
  1. 7.1Power dissipation in SoCs
  2. 7.2Thermal throttling and its effects
  3. 7.3Air and liquid cooling
  4. 7.4Heatsink design
  5. 7.5Thermal modelling of the unit
  6. 7.6Extreme automotive environments
  7. 7.7Temperature monitoring
  8. 7.8Dynamic thermal management
  9. 7.9Thermal validation in a climatic chamber
  10. 7.10Workshop: thermal simulation with Icepak
  1. 8.1System power budget
  2. 8.2Dynamic voltage and frequency scaling
  3. 8.3Low-power states
  4. 8.4Workload-based power management
  5. 8.5Impact on vehicle range
  6. 8.6Power supplies
  7. 8.7Energy efficiency of inference
  8. 8.8Optimising the power-performance trade-off
  9. 8.9Power consumption monitoring
  10. 8.10Lab: performance-power curve
  1. 9.1ISO 26262 parts 5 and 11
  2. 9.2SPFM and LFM metrics
  3. 9.3Lockstep and redundancy
  4. 9.4ECC and memory protection
  5. 9.5SoC safety monitors
  6. 9.6Hardware FMEDA
  7. 9.7Radiation-induced soft errors
  8. 9.8Freedom from interference
  9. 9.9Safety manuals
  10. 9.10Case study: FMEDA of an SoC
  1. 10.1Hypervisors on SoCs
  2. 10.2GPU partitioning
  3. 10.3Memory isolation
  4. 10.4Accelerator allocation
  5. 10.5Mixed criticality on a single SoC
  6. 10.6Containers on virtual machines
  7. 10.7Resource management
  8. 10.8Virtualisation performance
  9. 10.9Partitioning security
  10. 10.10Practical exercise: partitioning with a hypervisor
  1. 11.1MLPerf Automotive benchmarks
  2. 11.2Performance metrics
  3. 11.3Latency testing
  4. 11.4Thermal testing under sustained load
  5. 11.5Platform comparison
  6. 11.6Evaluation methodology
  7. 11.7Profiling tools
  8. 11.8Performance reports
  9. 11.9Decision-making
  10. 11.10Workshop: benchmark of an AD pipeline
  1. 12.1Definition of the workload
  2. 12.2Platform selection
  3. 12.3Mapping tasks to accelerators
  4. 12.4Inference optimisation
  5. 12.5Scheduling and real time
  6. 12.6Thermal and power management
  7. 12.7System evaluation
  8. 12.8Conclusions and future work
  9. 12.9Thesis report
  10. 12.10Master's Thesis: defence before a panel
Methodology, software & labs

How you'll learn

Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so the programme can be combined with work.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is CUDA, NVIDIA TensorRT, Apache TVM, ANSYS Icepak and Nsight Systems, in free, academic or evaluation versions. Exercises are based on real procedures for profiling inference workloads, thermal testing of compute units and benchmarking driving platforms. Assessment is continuous by module, plus the final Master's Thesis.

Standards covered: ISO 26262, AEC-Q100, ISO 21448, ISO/SAE 21434, IEC 61508, JEDEC JESD51, ISO 16750-4, MISRA C++:2023.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of ISO 26262, AEC-Q100 and ISO 21448 applied to real cases, not as a theoretical annex.
Industry software:CUDA, NVIDIA TensorRT, Apache TVM, ANSYS Icepak and Nsight Systems, in free, academic or evaluation versions.
Master's Thesis with defence:A complete heterogeneous computing project, from workload definition and platform selection to task mapping, inference optimisation, scheduling and thermal and power management, defended before a panel.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Define the workload
Characterise the perception, prediction and planning workloads and their latency budgets.
Select the platform
Compare automotive SoCs and choose the platform for the use case.
Map and optimise inference
Map tasks to CPU, GPU and NPU and optimise models with TensorRT or TVM.
Schedule and budget
Analyse real-time scheduling and define thermal and power budgets.
Master's Thesis
Evaluate the complete system through benchmarking and draw conclusions, defended before a panel.
Career opportunities

Where this takes you

Computing Platform EngineerInference Optimisation EngineerAutomotive Hardware ArchitectEmbedded Systems EngineerPerformance EngineerHardware Functional Safety Engineer
Admissions & scholarships

Requirements

  • A university degree in engineering, science or architecture, or equivalent demonstrable professional experience.
  • An internet connection and a computer capable of running the programme's software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with CUDA, NVIDIA TensorRT, Apache TVM, ANSYS Icepak and Nsight Systems, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.

A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme's software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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