Master’s in Analogue and Mixed-Signal Design Engineering
Online master's programme of 1,900 hours in analogue and mixed-signal design engineering. 12 modules covering analogue devices, CMOS amplifiers, noise and precision, references and integrated power management, filters, mixed-signal circuits, analogue layout, AMS verification, sensor interfaces and characterisation, with an assigned technical tutor.
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Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Analyse the behaviour of MOS and bipolar devices in analogue circuits.
Design amplifiers, references and biasing circuits.
Design continuous-time and switched filters and blocks.
Integrate analogue and digital blocks into mixed-signal systems.
Apply analogue layout techniques to minimise mismatch and noise.
Verify designs against process, voltage and temperature variations.
Characterise circuits in the laboratory and in production.
Who it's for
- Analogue design engineers seeking to strengthen their transistor-level skills.
- Mixed-signal design engineers working on converters, PLLs and interfaces.
- Analogue layout engineers focused on matching and parasitics.
- AMS verification engineers using Verilog-AMS and real-number models.
- IC characterisation engineers in the lab or in production test.
- Analogue applications engineers supporting customers and datasheets.
- Engineering or science graduates seeking to move into the semiconductor industry.
What you'll work with
- IEEE 1241 (terminology and test methods for analogue-to-digital converters)
- IEC 60747 (semiconductor devices)
- JEDEC JESD22 (reliability test methods)
- IEC 61000-4-2 (electrostatic discharge immunity)
- AEC-Q100 (qualification of integrated circuits for automotive)
- IEEE 1076.1 VHDL-AMS (analogue and mixed-signal hardware description language)
- ISO 26262-11 (application to semiconductors)
- IEEE 1800 SystemVerilog (hardware design and verification language)
- Cadence Virtuoso
- Spectre
- LTspice
- Keysight ADS
- MATLAB
12 modules · 1900 h
1.1MOS transistor model in strong and weak inversion1.2gm, ro and gm/Id efficiency parameters1.3Bipolar transistors and their small-signal model1.4Short-channel effects in advanced technologies1.5Integrated resistors and capacitors1.6Process design kits (PDKs)1.7Process variations and corners1.8Mismatch and Pelgrom's law1.9gm/Id sizing methodology1.10Practical: transistor characterisation with Spectre
2.1Common-source and cascode amplifiers2.2Current mirrors and their accuracy2.3Differential pairs and active load2.4Output stages2.5Supply-independent biasing2.6Frequency response of stages2.7Gain, bandwidth and poles2.8Small-signal analysis2.9AC and transient simulation2.10Lab: design of a cascode current mirror
3.1Two-stage Miller topology3.2Telescopic and folded-cascode amplifiers3.3Common-mode feedback3.4Stability and phase margin3.5Miller and nulling-resistor compensation3.6Slew rate and settling time3.7Rail-to-rail output amplifiers3.8Specifications and design trade-offs3.9Open-loop stability simulation3.10Workshop: design of a two-stage amplifier
4.1Thermal and flicker noise4.2Circuit noise analysis4.3Chopper stabilisation techniques4.4Auto-zeroing and offset cancellation4.5Mismatch and random offset4.6Harmonic distortion and intermodulation4.7Power supply rejection (PSRR)4.8Common-mode rejection (CMRR)4.9Noise and Monte Carlo simulation4.10Practical: noise optimisation of a preamplifier
5.1Bandgap voltage references5.2Current references5.3Temperature compensation5.4LDO linear regulators5.5LDO regulator stability5.6Integrated switching converters5.7Charge pumps5.8Start-up and supervisory circuits5.9Thermal and overcurrent protection5.10Lab: design of a bandgap reference
6.1Continuous-time active filters6.2Gm-C transconductance filters6.3Switched-capacitor filters6.4Anti-aliasing and reconstruction filters6.5Automatic filter tuning6.6Sensitivity to component variations6.7Noise in integrated filters6.8Complex filters for receivers6.9Filter synthesis with MATLAB6.10Case study: anti-aliasing filter for a converter
7.1Comparators and latches7.2Sample-and-hold circuits7.3Resistor and current-steering digital-to-analogue converters7.4Analogue-to-digital converter architectures7.5Oscillators and PLLs7.6Clock generation and jitter7.7Interfaces between analogue and digital domains7.8Digital noise coupling into the substrate7.9Digital calibration of analogue blocks7.10Workshop: design of a dynamic comparator
8.1Common-centroid techniques8.2Interdigitation and dummy devices8.3Guard rings and isolation8.4Routing of sensitive signals8.5Parasitic effects and extraction8.6Electromigration and metal widths8.7ESD protection at the inputs8.8DRC and LVS checks8.9Post-layout simulation with parasitics8.10Practical: layout of a differential pair
9.1Analogue verification plans9.2Simulation across process corners9.3Monte Carlo analysis9.4Behavioural modelling in Verilog-AMS9.5Co-simulation of analogue and digital blocks9.6Real-number models in SystemVerilog9.7AMS verification regressions9.8Coverage in analogue verification9.9Verification of low-power modes9.10Lab: co-simulation of a converter
10.1Integrated instrumentation amplifiers10.2Interfaces for capacitive sensors10.3Transimpedance amplifiers for photodiodes10.4Front-ends for resistive bridge sensors10.5Excitation and readout of inductive sensors10.6Low-noise biomedical front-ends10.7Input protection against overvoltage10.8Ultra-low power in autonomous nodes10.9Design for automotive and harsh environments10.10Workshop: front-end for a pressure sensor
11.1Evaluation and characterisation boards11.2Noise and distortion measurement11.3Offset and drift measurement11.4JEDEC reliability tests11.5AEC-Q100 automotive qualification11.6Production testing and trimming11.7Manufacturing yield11.8Silicon failure analysis11.9Datasheet documentation11.10Case study: characterisation plan for an amplifier
12.1Definition of the block to be designed12.2Specifications and architecture12.3Transistor-level design12.4Corner and Monte Carlo simulation12.5Circuit layout12.6Post-layout simulation with parasitics12.7Characterisation plan12.8Conclusions and future work12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so it fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Cadence Virtuoso, Spectre, LTspice, Keysight ADS and MATLAB, in free, academic or evaluation versions. Work is based on real procedures: design and simulation of CMOS operational amplifiers, characterisation of circuits across process corners and verification of mixed-signal circuits. Assessment is continuous per module, plus the final Master's Thesis.
Standards covered: IEEE 1241, IEC 60747, JEDEC JESD22, IEC 61000-4-2, AEC-Q100, IEEE 1076.1 VHDL-AMS, ISO 26262-11, IEEE 1800 SystemVerilog.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Cadence Virtuoso, Spectre, LTspice, Keysight ADS and MATLAB, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software, and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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