Diploma in Precision Clocking and Jitter Budgeting
Online postgraduate diploma of 800 hours in precision clocking and jitter budgeting. 8 modules covering jitter decomposition, clock tree architecture, jitter budgets, clocks for data converters, network synchronisation, jitter measurement and robust board design, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Decompose jitter into its random and deterministic components.
Design clock trees with suitable buffers and signalling standards.
Prepare jitter budgets for serial interfaces.
Specify sampling clocks for data converters.
Apply Synchronous Ethernet and PTP in telecommunication networks.
Measure jitter with instrumentation and correlated methods.
Design boards that are robust against clock degradation.
Who it's for
- Clock design engineers building timing architectures.
- Signal integrity engineers who need rigorous jitter budgets for serial links.
- Network synchronisation engineers working with SyncE and PTP.
- Hardware engineers responsible for clock distribution on complex boards.
- Interface validation engineers measuring jitter on PCIe and Ethernet.
- Telecommunications engineers deploying 5G timing and fronthaul.
- Engineering or science graduates seeking to enter telecommunications.
What you'll work with
- ITU-T G.8262 (timing characteristics of synchronous Ethernet equipment clocks)
- ITU-T G.8273.2 (timing characteristics of telecom boundary and slave clocks)
- IEEE 1588-2019 (Precision Time Protocol)
- ITU-T G.8275.1 (PTP telecom profile for phase/time synchronisation)
- PCI Express Base Specification 5.0 (PCIe interface and jitter requirements)
- IEEE 802.3-2022 (Ethernet)
- JEDEC JESD65B (definition of skew specifications)
- IEEE 1139-2022 (frequency and time metrology definitions)
- Skyworks ClockBuilder Pro
- TI Clock Tree Architect
- Keysight EZJIT
- PCI-SIG SigTest
8 modules
1.1Random and deterministic jitter1.2Periodic jitter, DDJ and ISI1.3Period, cycle-to-cycle and TIE jitter1.4Dual-Dirac model and BER extrapolation1.5Distributions and Gaussian tails1.6Bathtub curves and target error rate1.7Wander and how it differs from jitter1.8Units: UI, ps RMS and peak-to-peak1.9Source jitter and transfer jitter1.10Lab: RJ/DJ decomposition with an oscilloscope
2.1Reference sources: XO, TCXO and OCXO2.2Clock generators and synthesisers2.3Fan-out buffers and their additive jitter2.4LVDS, LVPECL, HCSL and CML standards2.5Terminations and AC/DC coupling2.6Spread spectrum clocking2.7Distribution on the board and between cards2.8Skew and its control2.9Clock tree design tools2.10Practical exercise: clock tree with ClockBuilder Pro
3.1Jitter budgeting methodology3.2Root-sum-square and linear summation3.3Receiver transfer functions3.4PCIe and Ethernet jitter masks3.5Integrated jitter by offset bands3.6Contribution of sources, buffers and channel3.7Margins and acceptance criteria3.8Budget spreadsheets3.9Review with suppliers3.10Workshop: jitter budget for a PCIe Gen5 link
4.1SNR limited by aperture jitter4.2Requirements for direct-sampling ADCs4.3Dual-loop jitter cleaners4.4Multi-device synchronisation and SYSREF4.5Low-noise differential distribution4.6Close-in and far-out phase noise4.7Integrating noise over the band4.8Effect of spurs on the spectrum4.9Component selection4.10Practical exercise: impact of jitter on a 14-bit ADC
5.1Synchronous Ethernet according to ITU-T G.82625.2PTP IEEE 1588 and telecom profiles5.3T-BC boundary clocks according to G.8273.25.4Holdover and oscillator stability5.5Phase requirements in 5G5.6Synchronisation architectures in fronthaul5.7Wander, MTIE and TDEV5.8Clock recovery and network PLLs5.9Synchronisation monitoring5.10Lab: MTIE and TDEV measurement
6.1Real-time and sampling oscilloscopes6.2Phase noise analysers for clocks6.3TIE methods and spectral analysis6.4EZJIT and SigTest tools6.5Instrument noise floor6.6Probes and fixtures6.7Correlation between methods6.8Measuring additive jitter6.9Measuring skew between outputs6.10Case study: comparison of measurement methods
7.1PLL power supply and decoupling7.2Coupling between clocks and crosstalk7.3Differential clock routing7.4Sensitivity to temperature and vibration7.5Immunity to switching noise7.6Clock failures and reference switching7.7Link errors caused by the clock7.8Clock design review7.9Clock tree documentation7.10Practical exercise: reducing jitter caused by power supply noise
8.1Definition of interfaces and clocks8.2Clock tree architecture8.3Jitter budget per interface8.4Selection of clock components8.5Simulation and analysis8.6Validation measurements8.7Margin report8.8Proposed design improvements8.9Report and presentation8.10Final project: final review with your tutor
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable materials, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, making it compatible with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Skyworks ClockBuilder Pro, TI Clock Tree Architect, Keysight EZJIT and PCI-SIG SigTest, in free, academic or evaluation versions. Tests are studied on real procedures for jitter decomposition with an oscilloscope, MTIE and TDEV measurement in network synchronisation, and jitter budgets for serial links. Assessment is continuous by module plus the final project.
Standards covered: ITU-T G.8262, ITU-T G.8273.2, IEEE 1588-2019, ITU-T G.8275.1, PCI Express Base Specification 5.0, IEEE 802.3-2022, JEDEC JESD65B, IEEE 1139-2022.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Skyworks ClockBuilder Pro, TI Clock Tree Architect, Keysight EZJIT and PCI-SIG SigTest, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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