Diploma in Model Compression and Inference in MCU/NPUs
Online postgraduate diploma of 800 hours in model compression and inference on MCUs/NPUs. 8 modules covering edge inference hardware, efficient architectures, quantisation, pruning and distillation, compilers and runtimes, on-device validation and product integration, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Select inference hardware according to memory and energy constraints.
Design efficient network architectures for microcontrollers.
Apply post-training quantisation and quantisation-aware training.
Reduce models through pruning and knowledge distillation.
Compile and deploy models with embedded runtimes.
Validate accuracy, latency and power consumption on the device.
Integrate inference into maintainable industrial products.
Who it's for
- TinyML engineers squeezing neural networks into kilobytes of memory.
- Embedded systems engineers adding inference to their firmware.
- Edge machine learning engineers deploying models outside the cloud.
- Firmware developers integrating models with RTOS and sensor drivers.
- IoT product engineers designing smart, low-power nodes.
- Model efficiency researchers working on quantisation, pruning and distillation.
- Engineering or science graduates looking to move into consumer electronics.
What you'll work with
- MLCommons MLPerf Tiny (benchmark for TinyML systems)
- ONNX 1.x (Open Neural Network Exchange)
- ISO/IEC 23053:2022 (framework for AI systems using ML)
- IEC 61508 (functional safety)
- Regulation (EU) 2024/2847 (Cyber Resilience Act)
- ETSI EN 303 645 (cyber security for consumer IoT devices)
- TensorFlow Lite Micro
- STM32Cube.AI
- Edge Impulse
- Apache TVM
- ONNX Runtime
8 modules
1.1Cortex-M and RISC-V microcontrollers1.2Flash memory, SRAM and their limits1.3NPUs: Ethos-U, Coral Edge TPU and Hailo1.4Accelerators in SoCs and DSPs1.5SIMD instructions and CMSIS-NN1.6Energy consumption and budget1.7Metrics: latency, MACs and peak memory1.8TinyML: industrial use cases1.9Platform selection1.10Workshop: memory profiling of a model on an MCU
2.1Depthwise separable convolutions2.2MobileNet and EfficientNet-Lite2.3Networks for audio and vibration on MCUs2.4Constrained neural architecture search (NAS)2.5MCUNet and hardware-aware design2.6Single-stage models for vision2.7Input size and resolution2.8Depth versus width2.9MLPerf Tiny benchmarks2.10Practical exercise: training a compact keyword-spotting model
3.1Fixed-point and int8 representation3.2Static and dynamic post-training quantisation3.3Calibration with representative data3.4Per-channel and per-tensor quantisation3.5Quantisation-aware training3.64-bit and binary quantisation3.7Quantisation errors and their analysis3.8Unsupported operators3.9Quantisation of transformer models3.10Lab: int8 quantisation with TensorFlow Lite
4.1Unstructured magnitude pruning4.2Structured pruning of channels and filters4.3Lottery ticket hypothesis4.4Sparsity and its exploitation in hardware4.5Knowledge distillation4.6Distillation of intermediate features4.7Low-rank factorisation4.8Combining pruning, distillation and quantisation4.9Accuracy recovery4.10Practical exercise: structured pruning and fine-tuning
5.1TensorFlow Lite Micro5.2ONNX Runtime and ExecuTorch5.3Apache TVM compiler5.4Vela for Ethos-U5.5Edge Impulse and STM32Cube.AI5.6Operator fusion5.7Tensor memory planning5.8Custom operators in the runtime5.9C code generation5.10Lab: deployment on STM32 with Cube.AI
6.1Numerical parity between PC and device6.2Latency measurement in cycles6.3Energy consumption measurement6.4Testing on development boards6.5Robustness to sensor variations6.6Model regression testing6.7Per-layer profiling6.8Trade-offs between accuracy, latency and energy6.9Validation report6.10Case study: vibration anomaly detector on an MCU
7.1Firmware architecture with inference7.2Real-time operating systems7.3Sensor buffer management7.4Updating models in the field7.5Model and firmware security7.6Certification and product requirements7.7Life-cycle maintenance7.8Hardware costs at scale7.9Industrial TinyML cases7.10Workshop: specification of a smart node
8.1Use case and constraints8.2Hardware selection8.3Reference model8.4Model compression8.5Compilation and deployment8.6On-device validation8.7Trade-off analysis8.8Product proposal8.9Report and presentation8.10Final project: final review with the tutor
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so the programme fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is TensorFlow Lite Micro, STM32Cube.AI, Edge Impulse, Apache TVM and ONNX Runtime, in free, academic or evaluation versions. Exercises are based on real procedures: measuring latency and power consumption on development boards, comparing quantisation and pruning techniques, and numerical parity testing between PC and microcontroller. Assessment is continuous by module, plus the final capstone project.
Standards covered: MLCommons MLPerf Tiny, ONNX 1.x, ISO/IEC 23053:2022, IEC 61508, Regulation (EU) 2024/2847, ETSI EN 303 645.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- An internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with TensorFlow Lite Micro, STM32Cube.AI, Edge Impulse, Apache TVM and ONNX Runtime, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector; no university degree is required.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
Related programmes
Diploma in Vibration/Acoustic Analysis and Health Index
Online postgraduate diploma of 800 hours in vibration/acoustic analysis and Health Index. 8 modules covering rotating machinery dynamics, vibro-acoustic acquisition, vibration, acoustic and ultrasound analysis, indicator…
Diploma in Security Policies and Stability in RL
Online postgraduate diploma of 800 hours in policy safety and stability in RL: 8 modules covering risks in reinforcement learning, constrained RL, shields and safety filters,…
Diploma in Vision-Assisted GD&T and Dimensional Control
Online postgraduate diploma of 800 hours in vision-assisted GD&T and dimensional inspection. 8 modules covering the GD&T language, machine vision for metrology, geometric tolerance evaluation, in-line…
More in Data, AI, Simulation & Analytics
All Data, AI, Simulation & Analytics programmes → · How to apply · Fees & financing · Scholarships