Diploma in Mixed-Criticality and Temporal Verification
Online postgraduate diploma of 800 hours in mixed-criticality and timing verification. 8 modules covering mixed-criticality scheduling, multicore interference, temporal partitioning, model-based and measurement-based timing verification and certification with EASA AMC 20-193, RTCA DO-178C and ISO 26262-6, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Explain the models and challenges of mixed-criticality systems.
Apply AMC and EDF-VD scheduling algorithms.
Characterise and mitigate interference in multicore processors.
Configure temporal partitioning and budget supervision.
Verify timing properties with timed automata.
Obtain timing evidence through hardware tracing.
Build certification arguments for mixed-criticality platforms.
Who it's for
- Critical-software engineers moving into multicore and mixed-criticality platforms.
- Timing verification engineers who need formal and measurement-based methods.
- IMA platform architects responsible for partitioning and consolidation.
- Aeronautical certification engineers working with AMC 20-193 and DO-178C.
- Functional safety engineers in automotive and rail.
- Real-time systems researchers seeking an industrial perspective.
- Engineering or science graduates looking to enter the aerospace sector.
What you'll work with
- EASA AMC 20-193 (use of multicore processors in airborne systems)
- RTCA DO-178C (airborne software certification)
- ISO 26262-6:2018 (automotive functional safety, software level)
- ARINC 653 (avionics partitioned operating systems)
- RTCA DO-297 (integrated modular avionics)
- RTCA DO-333 (formal methods supplement)
- IEC 61508-3:2010 (functional safety, software requirements)
- UPPAAL
- Rapita RVS
- AbsInt TimeWeaver
- Lauterbach TRACE32
8 modules
1.1DAL and ASIL levels on a single platform1.2Consolidation and SWaP reduction1.3Vestal model with multiple WCETs1.4Criticality modes and mode switching1.5Spatial and temporal isolation1.6Interference between applications1.7IMA and zonal architectures1.8Challenges of incremental certification1.9Open research lines1.10Case study: consolidation of avionics functions
2.1AMC algorithm and response-time analysis2.2EDF-VD with virtual deadlines2.3Dropping low-criticality tasks2.4Graceful service degradation2.5Scheduling by time partitions2.6Reservation servers and budgets2.7Mixed criticality in multicore scheduling2.8Recovery after a mode switch2.9Evaluation by simulation2.10Practical exercise: AMC analysis of a task set
3.1Interference channels according to AMC 20-1933.2Shared cache and partitioning3.3Memory controllers and DRAM banks3.4Interconnect and bus arbitration3.5Bandwidth regulation with MemGuard3.6Performance counters to measure interference3.7Stress microbenchmarks3.8Hardware and software mitigations3.9Worst case under resource contention3.10Lab: measuring interference with microbenchmarks
4.1ARINC 653 temporal partitioning4.2Partition scheduling tables4.3Budget monitors and watchdogs4.4Separation hypervisors4.5Deadline supervision in AUTOSAR4.6Overrun detection and containment4.7Health management and recovery4.8Inter-partition communication4.9Configuration and verification of tables4.10Workshop: partition table with a budget monitor
5.1Timed automata and networks of automata5.2Model checking with UPPAAL5.3Specification in TCTL temporal logic5.4Modelling schedulers and tasks5.5State explosion and abstraction5.6Verification of timed protocols5.7Formal methods according to DO-3335.8Counterexample generation5.9Integration with classical analysis5.10Practical exercise: UPPAAL model of a scheduler
6.1Hardware tracing with ETM and Nexus6.2Capture with Lauterbach TRACE326.3Timing coverage and scenarios6.4Timing analysis with Rapita RVS6.5Timing analysis with TimeWeaver6.6Timing distributions and extreme values6.7Stress testing with interference6.8Correlation between model and measurement6.9Management of test evidence6.10Lab: ETM tracing of a critical application
7.1AMC 20-193 objectives7.2Software and verification plans7.3Modular integration according to DO-2977.4Functional safety and ISO 262627.5Safety arguments with GSN7.6Common-mode failure analysis7.7Tool qualification7.8Change management and reverification7.9Interaction with the certification authority7.10Case study: safety argument for a zonal ECU
8.1Functions and criticality levels8.2Partitioning architecture8.3Scheduling analysis8.4Interference characterisation8.5Formal model and verification8.6Measurements on a real platform8.7Timing safety argument8.8Certification plan8.9Report and presentation8.10Final project: final review with the tutor
How you'll learn
100% online training on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. No fixed timetables: you progress at your own pace within the intake, so it can be combined with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is UPPAAL, Rapita RVS, AbsInt TimeWeaver and Lauterbach TRACE32, in free, academic or evaluation versions. Testing is studied on real procedures: interference measurement on multicore platforms, verification of timed models with UPPAAL and hardware tracing of critical applications. Assessment is continuous by module plus the final project.
Standards covered: EASA AMC 20-193, RTCA DO-178C, ISO 26262-6:2018, ARINC 653, RTCA DO-297, RTCA DO-333, IEC 61508-3:2010.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with UPPAAL, Rapita RVS, AbsInt TimeWeaver and Lauterbach TRACE32, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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