Master’s in Analogue and Mixed-Signal Design
Online master's programme of 1,900 hours in analogue and mixed-signal design (ADC/DAC, PLL, references, low-noise): 12 modules covering devices for analogue design, basic blocks, operational amplifiers, filters, data converters, integrated power management, mixed-signal circuits, analogue layout, verification, board-level design and chip manufacturing and testing, with an assigned technical tutor.
Master’s in Analogue and Mixed-Signal Design — studying from the United Kingdom
Electronics and telecommunications form a significant part of the UK technology economy, with clusters in Cambridge, Bristol, Edinburgh, Belfast and the South East. Semiconductor design firms, defence electronics suppliers, telecom operators and Internet of Things companies all require embedded systems and communications engineers. Arm, headquartered in Cambridge, is a notable example of the design sector. Engineers work on hardware, firmware, signal processing and network infrastructure, often within regulated frameworks for radio and telecoms equipment.
Fees for the United Kingdom: £4,930 (Pound sterling), with instalments and employer sponsorship available.
Relevant bodies in the United Kingdom
Typical roles
Questions from the United Kingdom
Which UK bodies recognise electronics, embedded systems and telecom qualifications?
The Institution of Engineering and Technology (IET) is the main UK body for electronics, embedded systems and telecoms, and the British Computer Society (BCS) covers embedded software. Chartered and incorporated engineer titles are regulated through the Engineering Council. SEIUM's qualifications are private and not accredited by these bodies, so you should check with the IET how your study would be assessed.
Do UK electronics and telecoms employers hire people with private online qualifications?
UK electronics, semiconductor, telecoms and embedded systems employers usually assess candidates on practical design skill, hardware and software projects, and experience. A private qualification may help show specialist learning, but how much it counts depends on each employer. A portfolio of working embedded or telecoms projects is often decisive.
Is it realistic to study this online while working in the UK, and what level of English is needed?
Online study means you can keep your UK job and study from home, with no student visa required. Teaching is in English, so you need solid technical English. Your assigned technical tutor will help you plan your work. Fees are payable in instalments, and some employers offer training support, which varies by employer. Compare the programme hours with your schedule before enrolling.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Model devices for analogue design.
Design analogue blocks and operational amplifiers.
Design filters, oscillators and data converters.
Integrate power management and mixed-signal circuits.
Produce robust analogue layouts.
Verify designs against process variations.
Plan chip manufacturing and characterisation.
Who it's for
- Analogue circuit designers.
- Mixed-signal engineers.
- Analogue layout engineers.
- Analogue verification engineers.
- Characterisation engineers.
- Power management designers.
- Engineering or science graduates seeking to enter the semiconductor industry.
What you'll work with
- AEC-Q100 (stress test qualification for automotive integrated circuits)
- JEDEC JESD22-A114 (ESD sensitivity testing, human body model)
- IEEE 1241 (terminology and test methods for ADCs)
- IEEE 1076.1 (VHDL-AMS) (analogue and mixed-signal hardware description language)
- IEC 60747-1 (semiconductor devices, general)
- ISO 26262-11 (application of ISO 26262 to semiconductors)
- Cadence Virtuoso
- Spectre
- LTspice
- Siemens Calibre
- KLayout
12 modules
1.1MOS transistor physics1.2Large-signal models1.3Small-signal models1.4Weak inversion region1.5Bipolar transistors1.6Short-channel effects1.7Thermal and flicker noise1.8Process variability1.9CMOS and BiCMOS technologies1.10Case study: characterising a transistor in simulation
2.1Current sources and mirrors2.2Single-stage amplifiers2.3Cascode and folded cascode2.4Differential pairs2.5Active loads2.6Bandgap voltage references2.7Biasing2.8Frequency response2.9The gm/Id methodology2.10Lab: designing a cascode mirror in Cadence
3.1Two-stage amplifier3.2Miller compensation3.3Stability and phase margin3.4Fully differential amplifiers3.5Common-mode feedback3.6Slew rate and bandwidth3.7Rail-to-rail3.8Low-noise amplifiers3.9Low-power amplifiers3.10Practical exercise: designing a two-stage OTA
4.1Active RC filters4.2gm-C filters4.3Switched-capacitor filters4.4Tuning and calibration4.5Integrators4.6RC and LC oscillators4.7Comparators4.8Sampling circuits4.9Distortion and linearity4.10Lab: switched-capacitor filter
5.1ADC and DAC specifications5.2SAR ADCs5.3Sigma-delta ADCs5.4Pipeline ADCs5.5Capacitive DACs5.6Quantisation noise5.7Calibration5.8Performance measurements5.9Architectures for sensors5.10Practical exercise: 10-bit SAR ADC at block level
6.1Integrated LDO regulators6.2Integrated DC-DC converters6.3Charge pumps6.4Precision references6.5Reset and supervisors6.6Battery management6.7Energy harvesting6.8Light-load efficiency6.9Protections6.10Lab: capacitor-less LDO
7.1PLLs and frequency synthesis7.2DLLs7.3Voltage-controlled oscillators7.4Phase detectors7.5Clock recovery7.6Sensor interfaces7.7Basic RF front-ends7.8Analogue-digital integration7.9Substrate noise7.10Practical exercise: integer-N PLL in simulation
8.1Design rules8.2Device matching8.3Common centroid and interdigitation8.4Guard rings8.5Well proximity and stress effects8.6Parasitics and extraction8.7ESD protection8.8Chip floorplanning8.9DRC and LVS verification8.10Lab: layout of a matched differential pair
9.1Corner simulation9.2Monte Carlo9.3Ageing analysis9.4Post-layout simulation9.5Mixed-signal verification9.6Verilog-AMS behavioural models9.7Functional safety verification9.8Verification coverage9.9Design reviews9.10Practical exercise: Monte Carlo of a bandgap
10.1Selecting discrete amplifiers10.2Sensor signal conditioning10.3Instrumentation amplifiers10.4Anti-aliasing filters10.5External references and ADCs10.6Mixed-signal PCB layout10.7Grounding and shielding10.8Board-level SPICE simulation10.9Laboratory measurements10.10Workshop: front-end for a strain gauge bridge
11.1Tape-out flow11.2Multi-project wafers11.3Packaging11.4Production testing11.5Laboratory characterisation11.6Measurement benches11.7Failure analysis11.8Reliability and AEC-Q100 qualification11.9Product documentation11.10Case study: characterisation plan for a chip
12.1Block specification12.2Architecture12.3Transistor-level design12.4Simulations12.5Layout12.6Extraction and post-layout12.7Robustness verification12.8Test plan12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
100% online programme on the SEIUM campus, with downloadable material, recorded lectures and an assigned technical tutor. No fixed timetables: you progress at your own pace within each intake, so it fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Cadence Virtuoso, Spectre, LTspice, Siemens Calibre and KLayout, in free, academic or evaluation versions. Testing is studied on real procedures: corner and Monte Carlo simulations, laboratory chip characterisation and noise and linearity measurements. Assessment is continuous by module, plus the final Master's Thesis.
Standards covered: AEC-Q100, JEDEC JESD22-A114, IEEE 1241, IEEE 1076.1 (VHDL-AMS), IEC 60747-1, ISO 26262-11.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Cadence Virtuoso, Spectre, LTspice, Siemens Calibre and KLayout, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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