Diploma in RMA/EDF Scheduling and WCET Analysis
Online postgraduate diploma of 800 hours in RMA/EDF Scheduling and WCET Analysis: 8 modules covering real-time system models, Rate Monotonic and EDF scheduling, shared resources and synchronisation, multicore scheduling, WCET analysis, and timing verification and certification, with an assigned technical tutor.
Diploma in RMA/EDF Scheduling and WCET Analysis — studying from Singapore
Singapore is one of Asia's leading electronics manufacturing centres, with semiconductor fabrication, back-end assembly and test, and precision electronics concentrated in areas such as Tampines and Jurong. The sector also includes embedded systems for industrial and automotive use and a strong telecommunications base led by the Infocomm Media Development Authority. Major employers include global semiconductor firms and electronics manufacturers. Engineers work on hardware design, firmware, communications systems and test engineering.
Fees for Singapore: S$1,840 (Singapore dollar), with instalments and employer sponsorship available.
Relevant bodies in Singapore
Typical roles
Questions from Singapore
How are electronics and telecom engineers recognised in Singapore, and does SEIUM count?
Telecom and electronics engineering is regulated by the Infocomm Media Development Authority (IMDA), and engineers may register with the Professional Engineers Board (PEB). SEIUM's qualifications are private, not state degrees, and not accredited by any national body. Whether they are recognised is decided by employers or the relevant body, so confirm this before enrolling.
Which Singapore employers hire embedded systems and telecom engineers?
Singapore has demand from telecom operators, semiconductor and electronics manufacturers, defence and aerospace firms, and industrial automation companies. Employers generally assess hands-on skills in firmware, hardware design and testing. Your final project can evidence embedded or telecom competence, but its value is for each employer to judge.
Can I follow this from Singapore while working, and does it need a visa?
Yes, the programmes are 100% online and taught in English, so no student visa is needed to study from home in Singapore. Expect a heavy workload: 1,900 hours for a master's, 800 for a postgraduate diploma and 300 for a specialist course. Fees can be paid in instalments, and employer sponsorship is possible.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Model real-time systems through tasks, deadlines and priorities.
Analyse schedulability with RMA and response time analysis.
Apply EDF scheduling and bandwidth servers.
Manage shared resources with priority inheritance and ceiling protocols.
Evaluate scheduling on multicore platforms.
Estimate WCET using static, measurement-based and hybrid techniques.
Produce timing evidence for the certification of critical software.
Who it's for
- Real-time systems engineers who need rigorous schedulability analysis.
- Critical software engineers working to DO-178C, ISO 26262 or IEC 61508.
- Timing verification engineers measuring and bounding execution times.
- Embedded software architects designing task sets and priorities.
- Aeronautical certification engineers preparing multicore and timing evidence.
- Automotive software engineers working with OSEK and AUTOSAR scheduling.
- Engineering or science graduates looking to enter the aerospace sector.
What you'll work with
- ISO 26262-6:2018 (road vehicle functional safety at software level)
- RTCA DO-178C (software considerations in airborne systems certification)
- EASA AMC 20-193 (use of multicore processors in airborne systems)
- IEC 61508-3:2010 (functional safety software requirements)
- ISO 17356-3:2005 – OSEK/VDX OS (automotive real-time operating system)
- IEEE 1003.1 (POSIX real-time extensions)
- AbsInt aiT
- Rapita RVS
- MAST
- Cheddar
- Percepio Tracealyzer
8 modules
1.1Periodic, sporadic and aperiodic tasks1.2Deadlines, jitter and response time1.3Hard and soft real time1.4Cyclic scheduling and executives1.5Fixed versus dynamic priorities1.6Processor utilisation1.7The Liu and Layland task model1.8Timing requirements in critical systems1.9Formal notation of the task model1.10Lab: cyclic executive on a microcontroller
2.1RMA and DMA priority assignment2.2Liu and Layland utilisation bound2.3Bini's hyperbolic bound test2.4Response time analysis (RTA)2.5Arbitrary deadlines and the busy period2.6Release jitter and offsets2.7Audsley's optimal priority assignment2.8Context-switch overheads2.9Slack and aperiodic servers2.10Practical: RTA of a set of control tasks
3.1Optimality of EDF on a uniprocessor3.2Processor demand test3.3QPA analysis for constrained deadlines3.4Least Laxity First and variants3.5CBS and bandwidth servers3.6SCHED_DEADLINE in Linux3.7Overload and graceful degradation3.8Practical comparison of EDF and RMA3.9Implementing EDF in an RTOS3.10Lab: tasks with SCHED_DEADLINE
4.1Priority inversion and the Mars Pathfinder case4.2Priority inheritance protocol4.3Priority ceiling protocol (PCP)4.4Stack Resource Policy4.5Blocking and calculation of the B term4.6Nested and non-nested critical sections4.7Non-blocking communication between tasks4.8Resources in OSEK and AUTOSAR4.9Interrupts and their inclusion in the analysis4.10Workshop: priority inversion in FreeRTOS
5.1Partitioned and global scheduling5.2Bin-packing allocation heuristics5.3Global EDF and the Dhall effect5.4Interference from shared resources5.5Contention in cache, buses and memory5.6AMC 20-193 requirements5.7Scheduling in multicore AUTOSAR5.8Task migration and affinity5.9Response time on multicore5.10Practical: partitioning tasks across four cores
6.1Definition of WCET, BCET and pessimism6.2Static analysis: control flow and loops6.3Cache and pipeline modelling6.4Abstract interpretation in aiT6.5Measurement-based analysis6.6Hybrid approaches with Rapita RVS6.7MBPTA and probabilistic techniques6.8Annotations and loop bounds6.9Influence of the compiler on WCET6.10Lab: static analysis of a task with aiT
7.1Timing tracing with Tracealyzer7.2Measuring latencies and interrupts7.3Scheduling simulation with Cheddar7.4Schedulability analysis with MAST7.5Timing evidence for DO-178C7.6ISO 26262 timing requirements7.7Timing margins and budgets7.8Stress and worst-case testing7.9Change management and re-analysis7.10Case study: timing dossier for a flight control system
8.1Definition of the system and its tasks8.2WCET estimation and measurement8.3Selection of the scheduling policy8.4System schedulability analysis8.5Implementation on an RTOS8.6Tracing and deadline verification8.7Timing margins report8.8Optimisation proposals8.9Report and presentation8.10Final project: final review with your tutor
How you'll learn
The programme is delivered 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so you can combine it with your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is AbsInt aiT, Rapita RVS, MAST, Cheddar and Percepio Tracealyzer, in free, academic or evaluation versions. Testing is studied through real procedures: schedulability analysis of control tasks, WCET measurement on microcontrollers and timing tracing with an RTOS. Assessment is continuous, module by module, plus the final project.
Standards covered: ISO 26262-6:2018, RTCA DO-178C, EASA AMC 20-193, IEC 61508-3:2010, ISO 17356-3:2005 (OSEK/VDX OS) and IEEE 1003.1 (POSIX real-time extensions).
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- An internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with AbsInt aiT, Rapita RVS, MAST, Cheddar and Percepio Tracealyzer, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the programme software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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