Master’s in SoC/FPGA Architectures for Embedded Systems
Online master's programme of 1,900 hours in SoC/FPGA architectures for embedded systems (HDL/HLS, AXI, DMA, verification). 12 modules covering digital logic and the FPGA flow, RTL design in VHDL and SystemVerilog, UVM verification, heterogeneous SoCs, AXI interconnect, high-level synthesis, RISC-V soft-cores, embedded Linux, hardware acceleration and functional safety, with an assigned technical tutor.
Master’s in SoC/FPGA Architectures for Embedded Systems — studying from Malta
Malta has a well-developed telecommunications sector, with a history of hosting submarine cable landing points and a substantial base of network and communications providers. The island's regulatory environment supports digital infrastructure, and this has encouraged companies in embedded systems, network engineering and electronics design. Employers include telecommunications operators, software and hardware developers, and multinational technology firms with Maltese engineering teams. Engineers with knowledge of wireless systems, network security and embedded programming find steady demand.
Fees for Malta: €9,930 (Euro), with instalments and employer sponsorship available.
Relevant bodies in Malta
Typical roles
Questions from Malta
How are electronics and telecom engineers recognised professionally in Malta?
Engineering titles in Malta are regulated by the Chamber of Engineers (KSU) under the Engineering Profession Act. Telecommunications is overseen by the Malta Communications Authority, which regulates licensing and spectrum. A SEIUM qualification is a private one, not a state degree and not accredited by a national body, so recognition depends on employers and the relevant authority.
Which Maltese employers hire embedded systems and telecom engineers?
Malta has telecoms operators, electronics manufacturers and component suppliers, iGaming and technology firms that use embedded hardware, and defence and maritime electronics companies. Employers typically assess hands-on design experience and certifications. A private qualification can help your profile, especially alongside practical projects.
Can I fit this programme around work, and what are the practical requirements?
The programme is 100% online and taught in English, with an assigned technical tutor. You can study from Malta without a student visa. Choose a course length that matches your available time, from 300 hours up to 1,900. Ask about fee instalments and employer sponsorship before enrolling.
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What you will be able to do
Design synthesisable digital architectures in VHDL and SystemVerilog.
Verify hardware designs with UVM, assertions and functional coverage.
Integrate processor subsystems and programmable logic through AXI.
Accelerate algorithms with high-level synthesis and hardware-software partitioning.
Develop embedded software and Linux drivers on SoC platforms.
Apply reliability and functional safety techniques in programmable logic.
Validate SoC systems on the board with performance and power measurements.
Who it's for
- FPGA design engineers moving into complete SoC architectures.
- Hardware verification engineers who want to master UVM and formal methods.
- SoC system architects looking for a deeper grounding in hardware-software integration.
- Embedded firmware developers who want to work closer to programmable logic.
- Hardware acceleration engineers working on vision, AI or signal processing.
- Airborne hardware engineers dealing with DO-254 and functional safety.
- Engineering or science graduates aiming to enter aerospace and defence.
What you'll work with
- IEEE 1076 (VHDL) (VHDL hardware description language)
- IEEE 1800 (SystemVerilog) (hardware design and verification language)
- IEC 61508 (functional safety of electrical/electronic/programmable systems)
- RTCA DO-254 (design assurance for airborne electronic hardware)
- IEEE 1149.1 (JTAG) (test access port and boundary scan)
- Arm AMBA AXI4 Specification (on-chip interconnect protocol)
- ISO 26262-11 (automotive functional safety applied to semiconductors)
- IEEE 1801 (UPF) (low-power design intent)
- AMD Vivado and Vitis
- Intel Quartus Prime
- Questa Advanced Simulator
- Verilator
- cocotb
12 modules
1.1Combinational and synchronous sequential logic1.2FPGA architecture: LUT, CLB and BRAM1.3DSP blocks and clock resources1.4Synthesis, place and route flow1.5Timing constraints in XDC and SDC1.6Static timing analysis and slack1.7Metastability and clock domain crossing1.8Synchronous and asynchronous reset strategies1.9Static and dynamic power consumption in FPGAs1.10Practical exercise: parameterisable counter with timing analysis
2.1Types, signals and processes in VHDL-20082.2Modules, interfaces and packages in SystemVerilog2.3Coded finite state machines2.4Design of synchronous and asynchronous FIFOs2.5Pipelining and retiming for maximum frequency2.6Inference of memories and multipliers2.7Synthesis-oriented coding2.8Parameterisation with generics and generate2.9RTL style guides and linting2.10Lab: UART controller with FIFO in VHDL
3.1Self-checking testbenches in SystemVerilog3.2UVM methodology: agents, sequences and scoreboards3.3Verification with cocotb in Python3.4SVA assertions and functional coverage3.5Constrained-random stimulus generation3.6Formal verification with SymbiYosys3.7Simulation with Questa, Vivado Sim and Verilator3.8Verification plan and coverage closure3.9Automated regressions in continuous integration3.10Practical exercise: UVM testbench for an AXI-Lite peripheral
4.1Zynq-7000, Zynq UltraScale+ and Versal families4.2Intel Agilex SoC and Cyclone V SoC4.3ARM Cortex-A and Cortex-R processing subsystem4.4PS-PL interconnect and high-performance ports4.5Memory hierarchy, caches and coherency4.6DDR4 and LPDDR4 controllers4.7Power management and power domains4.8Secure boot and chain of trust4.9Device selection according to requirements4.10Case study: sizing an SoC for vision applications
5.1AMBA AXI4, AXI4-Lite and AXI4-Stream protocols5.2Valid-ready handshake and backpressure5.3Burst transfers and alignment5.4DMA engines and scatter-gather5.5Crossbar interconnects and programmable NoC5.6Avalon and Wishbone as alternatives5.7Arbitration and quality of service5.8Design of peripherals with memory-mapped registers5.9Debugging with ILA and bus analysers5.10Lab: AXI-Stream peripheral with DMA
6.1From C++ to RTL with Vitis HLS6.2Pipeline, unroll and partition pragmas6.3m_axi, s_axilite and axis interfaces6.4Latency and initiation interval analysis6.5Fixed-point arithmetic with ap_fixed6.6Data flows with hls::stream and dataflow6.7Co-simulation between C model and RTL6.8Comparison with Intel HLS and Catapult6.9Design space exploration6.10Practical exercise: FIR filter accelerated through HLS
7.1MicroBlaze and Nios V on FPGA7.2Open RISC-V cores: VexRiscv and CVA67.3Custom instruction set extensions7.4Multiprocessor systems in programmable logic7.5Integration with LiteX and Migen7.6Bare-metal firmware for soft-cores7.7JTAG debugging with OpenOCD7.8Performance compared with hardened cores7.9Licensing and the RISC-V ecosystem7.10Lab: RISC-V SoC with a custom peripheral
8.1XSA hardware platforms and device tree8.2Bare-metal applications with standalone drivers8.3FreeRTOS on Cortex-R5 and Cortex-A538.4Linux with PetaLinux and Yocto8.5UIO drivers and platform drivers8.6Asymmetric multiprocessing with OpenAMP8.7Inter-core communication with RPMsg8.8Remote bitstream updates8.9Software profiling and bottlenecks8.10Practical exercise: Linux driver for an accelerator in the PL
9.1Hardware-software partitioning9.2Video processing with Vitis Vision9.3Neural network inference with Vitis AI9.4Quantisation and DPU in programmable logic9.5Signal processing on AI Engines9.6High-speed interfaces: PCIe and Ethernet9.7Serial transceivers and JESD204B/C9.8Throughput and latency measurement9.9Energy efficiency per operation9.10Case study: accelerating object detection
10.1Radiation effects: SEU and SEFI10.2Triple modular redundancy and scrubbing10.3Mitigation with the Soft Error Mitigation IP10.4Design to IEC 61508 in programmable logic10.5DO-254 requirements for airborne hardware10.6Bitstream encryption and authentication10.7Protection against side-channel attacks10.8Test access ports and IEEE 1149.1 boundary scan10.9Thermal management and ageing10.10Workshop: failure mode analysis of an FPGA design
11.1PCB design for high-density FPGAs11.2Signal integrity in DDR interfaces11.3Power integrity and decoupling11.4Regulator sequencing and PMICs11.5Hardware start-up and bring-up11.6Measurements with oscilloscope and logic analyser11.7Production testing and in-system programming11.8System electromagnetic compatibility11.9Design documentation and version control11.10Lab: bring-up of a Zynq UltraScale+ board
12.1Definition of the target embedded system12.2Requirements specification and architecture12.3Partitioning and block design12.4RTL or HLS implementation12.5Integration of the embedded software12.6Verification and on-board validation12.7Measurement of performance and resource usage12.8Analysis of results and improvements12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so the programme fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is AMD Vivado and Vitis, Intel Quartus Prime, Questa Advanced Simulator, Verilator and cocotb, in free, academic or evaluation versions. Real procedures are studied: UVM verification with functional coverage, laboratory bring-up of SoC boards and performance measurement of hardware accelerators. Assessment is continuous by module, plus the final Master's Thesis.
Standards covered: IEEE 1076 (VHDL), IEEE 1800 (SystemVerilog), IEC 61508, RTCA DO-254, IEEE 1149.1 (JTAG), Arm AMBA AXI4 Specification, ISO 26262-11, IEEE 1801 (UPF).
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with AMD Vivado and Vitis, Intel Quartus Prime, Questa Advanced Simulator, Verilator and cocotb, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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