Diploma in Timing Closure, Floorplanning and DFT
Online postgraduate diploma of 800 hours in Timing Closure, Floorplanning and DFT: 8 modules covering static timing analysis, timing closure techniques, chip and FPGA floorplanning, physical implementation, design for test, BIST and boundary scan, and sign-off for production, with an assigned technical tutor.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Analyse timing paths with STA across multiple corners and modes.
Apply timing closure techniques in ASIC and FPGA designs.
Plan the floorplan and power network of a chip.
Run a physical implementation flow through to sign-off.
Insert scan structures and generate patterns with ATPG.
Integrate BIST, boundary scan and IJTAG networks.
Prepare a design for tape-out and production test.
Who it's for
- Physical implementation engineers aiming to master the full back-end flow.
- STA engineers responsible for timing constraints and sign-off.
- DFT engineers working on scan, ATPG and BIST.
- ASIC back-end engineers preparing designs for tape-out.
- Semiconductor test engineers who need to understand DFT structures and yield.
- FPGA engineers facing demanding timing closure and floorplanning challenges.
- Engineering or science graduates looking to enter the semiconductor industry.
What you'll work with
- IEEE 1149.1-2013 – JTAG (boundary-scan test access port)
- IEEE 1500-2005 (embedded core test wrappers)
- IEEE 1687-2014 – IJTAG (access to embedded instruments)
- IEEE 1801-2018 – UPF (low-power design intent)
- IEEE 1149.6-2015 (boundary scan for AC-coupled and differential signals)
- ISO 26262-11:2018 (functional safety guidelines for semiconductors)
- Synopsys PrimeTime
- Cadence Innovus
- Siemens Tessent
- AMD Vivado
- OpenROAD
8 modules
1.1Timing paths: startpoints and endpoints1.2Setup, hold and slack1.3NLDM and CCS delay models1.4PVT corners and multi-mode analysis1.5On-chip variation: OCV, AOCV and POCV1.6SDC constraints: clocks and exceptions1.7False paths and multicycle paths1.8Interpreting timing reports1.9Clock skew, latency and uncertainty1.10Lab: SDC constraints for a multi-clock design
2.1Timing-driven synthesis2.2Retiming and register duplication2.3Logic restructuring and pipelining2.4Cell sizing and Vt swapping2.5Buffer insertion and hold fixing2.6Late-stage timing ECOs2.7Sign-off with parasitic extraction2.8Crosstalk and signal integrity analysis2.9FPGA closure: directives and pblocks2.10Practical: timing closure of a critical path
3.1Floorplan objectives and inputs3.2Die sizing and utilisation3.3Placement of macros and memories3.4Power rings and meshes3.5Hierarchical partitioning into blocks3.6Pins, I/O and bump planning3.7Placement regions and constraints3.8Early congestion analysis3.9FPGA floorplanning with pblocks3.10Workshop: floorplan of an SoC with SRAM memories
4.1Global and detailed placement4.2Clock tree synthesis (CTS)4.3Global and detailed routing4.4Physical verification with DRC and LVS4.5IR drop and electromigration analysis4.6Power optimisation and multi-Vt4.7Low-power design with UPF4.8Filler, tap and endcap cells4.9Open-source flow with OpenROAD4.10Lab: RTL-to-GDS flow with OpenROAD
5.1Fault models: stuck-at and transition5.2Controllability and observability5.3Scan chain insertion5.4Scan compression and EDT5.5DFT rules and typical violations5.6ATPG and fault coverage5.7At-speed patterns and test clocks5.8Impact of DFT on area and timing5.9Quality metrics and DPPM5.10Practical: scan insertion and ATPG
6.1Memory BIST and March algorithms6.2Logic BIST and LFSR generators6.3Boundary scan with IEEE 1149.16.4Core wrappers according to IEEE 15006.5IJTAG networks with IEEE 16876.6Memory repair and fuses6.7In-system and in-field test6.8ISO 26262 requirements for test6.9Diagnosis and wafer yield analysis6.10Lab: MBIST on an embedded memory
7.1Multi-corner, multi-mode sign-off7.2Final physical verification7.3Logic equivalence after ECO7.4Timing-annotated pattern simulation7.5Test programs on ATE7.6Yield learning and failure diagnosis7.7Silicon testing in the laboratory7.8Test cost and optimisation7.9Tape-out checklist7.10Case study: tape-out review of a block
8.1Design specification and constraints8.2Floorplan and power network8.3Implementation and timing closure8.4DFT insertion and ATPG8.5Coverage and area analysis8.6Sign-off verification8.7Report of the results obtained8.8Lessons learnt from the flow8.9Report and presentation8.10Final project: final review with your tutor
How you'll learn
The programme is delivered 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so you can combine it with your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Synopsys PrimeTime, Cadence Innovus, Siemens Tessent, AMD Vivado and OpenROAD, in free, academic or evaluation versions. Testing is studied through real procedures: multi-corner timing analysis, scan insertion and ATPG pattern generation, and timing closure on FPGA. Assessment is continuous, module by module, plus the final project.
Standards covered: IEEE 1149.1-2013 (JTAG), IEEE 1500-2005, IEEE 1687-2014 (IJTAG), IEEE 1801-2018 (UPF), IEEE 1149.6-2015 and ISO 26262-11:2018.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- An internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Synopsys PrimeTime, Cadence Innovus, Siemens Tessent, AMD Vivado and OpenROAD, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the programme software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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