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Postgraduate DiplomaElectronics, Embedded Systems & Telecom Applications open

Diploma in RMA/EDF Scheduling and WCET Analysis

Online postgraduate diploma of 800 hours in RMA/EDF Scheduling and WCET Analysis: 8 modules covering real-time system models, Rate Monotonic and EDF scheduling, shared resources and synchronisation, multicore scheduling, WCET analysis, and timing verification and certification, with an assigned technical tutor.

Duration6–8 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Model real-time systems through tasks, deadlines and priorities.

02

Analyse schedulability with RMA and response time analysis.

03

Apply EDF scheduling and bandwidth servers.

04

Manage shared resources with priority inheritance and ceiling protocols.

05

Evaluate scheduling on multicore platforms.

06

Estimate WCET using static, measurement-based and hybrid techniques.

07

Produce timing evidence for the certification of critical software.

Profile

Who it's for

  • Real-time systems engineers who need rigorous schedulability analysis.
  • Critical software engineers working to DO-178C, ISO 26262 or IEC 61508.
  • Timing verification engineers measuring and bounding execution times.
  • Embedded software architects designing task sets and priorities.
  • Aeronautical certification engineers preparing multicore and timing evidence.
  • Automotive software engineers working with OSEK and AUTOSAR scheduling.
  • Engineering or science graduates looking to enter the aerospace sector.
Standards & tools

What you'll work with

  • ISO 26262-6:2018 (road vehicle functional safety at software level)
  • RTCA DO-178C (software considerations in airborne systems certification)
  • EASA AMC 20-193 (use of multicore processors in airborne systems)
  • IEC 61508-3:2010 (functional safety software requirements)
  • ISO 17356-3:2005 – OSEK/VDX OS (automotive real-time operating system)
  • IEEE 1003.1 (POSIX real-time extensions)
  • AbsInt aiT
  • Rapita RVS
  • MAST
  • Cheddar
  • Percepio Tracealyzer
Syllabus

8 modules

  1. 1.1Periodic, sporadic and aperiodic tasks
  2. 1.2Deadlines, jitter and response time
  3. 1.3Hard and soft real time
  4. 1.4Cyclic scheduling and executives
  5. 1.5Fixed versus dynamic priorities
  6. 1.6Processor utilisation
  7. 1.7The Liu and Layland task model
  8. 1.8Timing requirements in critical systems
  9. 1.9Formal notation of the task model
  10. 1.10Lab: cyclic executive on a microcontroller
  1. 2.1RMA and DMA priority assignment
  2. 2.2Liu and Layland utilisation bound
  3. 2.3Bini's hyperbolic bound test
  4. 2.4Response time analysis (RTA)
  5. 2.5Arbitrary deadlines and the busy period
  6. 2.6Release jitter and offsets
  7. 2.7Audsley's optimal priority assignment
  8. 2.8Context-switch overheads
  9. 2.9Slack and aperiodic servers
  10. 2.10Practical: RTA of a set of control tasks
  1. 3.1Optimality of EDF on a uniprocessor
  2. 3.2Processor demand test
  3. 3.3QPA analysis for constrained deadlines
  4. 3.4Least Laxity First and variants
  5. 3.5CBS and bandwidth servers
  6. 3.6SCHED_DEADLINE in Linux
  7. 3.7Overload and graceful degradation
  8. 3.8Practical comparison of EDF and RMA
  9. 3.9Implementing EDF in an RTOS
  10. 3.10Lab: tasks with SCHED_DEADLINE
  1. 4.1Priority inversion and the Mars Pathfinder case
  2. 4.2Priority inheritance protocol
  3. 4.3Priority ceiling protocol (PCP)
  4. 4.4Stack Resource Policy
  5. 4.5Blocking and calculation of the B term
  6. 4.6Nested and non-nested critical sections
  7. 4.7Non-blocking communication between tasks
  8. 4.8Resources in OSEK and AUTOSAR
  9. 4.9Interrupts and their inclusion in the analysis
  10. 4.10Workshop: priority inversion in FreeRTOS
  1. 5.1Partitioned and global scheduling
  2. 5.2Bin-packing allocation heuristics
  3. 5.3Global EDF and the Dhall effect
  4. 5.4Interference from shared resources
  5. 5.5Contention in cache, buses and memory
  6. 5.6AMC 20-193 requirements
  7. 5.7Scheduling in multicore AUTOSAR
  8. 5.8Task migration and affinity
  9. 5.9Response time on multicore
  10. 5.10Practical: partitioning tasks across four cores
  1. 6.1Definition of WCET, BCET and pessimism
  2. 6.2Static analysis: control flow and loops
  3. 6.3Cache and pipeline modelling
  4. 6.4Abstract interpretation in aiT
  5. 6.5Measurement-based analysis
  6. 6.6Hybrid approaches with Rapita RVS
  7. 6.7MBPTA and probabilistic techniques
  8. 6.8Annotations and loop bounds
  9. 6.9Influence of the compiler on WCET
  10. 6.10Lab: static analysis of a task with aiT
  1. 7.1Timing tracing with Tracealyzer
  2. 7.2Measuring latencies and interrupts
  3. 7.3Scheduling simulation with Cheddar
  4. 7.4Schedulability analysis with MAST
  5. 7.5Timing evidence for DO-178C
  6. 7.6ISO 26262 timing requirements
  7. 7.7Timing margins and budgets
  8. 7.8Stress and worst-case testing
  9. 7.9Change management and re-analysis
  10. 7.10Case study: timing dossier for a flight control system
  1. 8.1Definition of the system and its tasks
  2. 8.2WCET estimation and measurement
  3. 8.3Selection of the scheduling policy
  4. 8.4System schedulability analysis
  5. 8.5Implementation on an RTOS
  6. 8.6Tracing and deadline verification
  7. 8.7Timing margins report
  8. 8.8Optimisation proposals
  9. 8.9Report and presentation
  10. 8.10Final project: final review with your tutor
Methodology, software & labs

How you'll learn

The programme is delivered 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so you can combine it with your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is AbsInt aiT, Rapita RVS, MAST, Cheddar and Percepio Tracealyzer, in free, academic or evaluation versions. Testing is studied through real procedures: schedulability analysis of control tasks, WCET measurement on microcontrollers and timing tracing with an RTOS. Assessment is continuous, module by module, plus the final project.

Standards covered: ISO 26262-6:2018, RTCA DO-178C, EASA AMC 20-193, IEC 61508-3:2010, ISO 17356-3:2005 (OSEK/VDX OS) and IEEE 1003.1 (POSIX real-time extensions).

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of ISO 26262-6, RTCA DO-178C and EASA AMC 20-193 applied to real cases, not as a theoretical annex.
Industry software:AbsInt aiT, Rapita RVS, MAST, Cheddar and Percepio Tracealyzer, in free, academic or evaluation versions.
Final project:a complete timing analysis of a real-time system, from WCET estimation and schedulability analysis to RTOS implementation and deadline verification, reviewed by your tutor.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

System and task definition
Define the system and its task set with timing requirements.
WCET estimation
Estimate and measure the WCET of each task.
Scheduling and schedulability
Select the scheduling policy and analyse system schedulability.
RTOS implementation and tracing
Implement the task set on an RTOS and verify deadlines through tracing.
Final project
Report timing margins and propose optimisations, reviewed by your tutor.
Career opportunities

Where this takes you

Real-time systems engineerCritical software engineerTiming verification engineerEmbedded software architectAeronautical certification engineerAutomotive software engineer
Admissions & scholarships

Requirements

  • Prior technical training or professional experience in the sector. No university degree is required.
  • An internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with AbsInt aiT, Rapita RVS, MAST, Cheddar and Percepio Tracealyzer, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.

Prior technical training or professional experience in the sector (no university degree required), a computer able to run the programme software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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