Diploma in Interface JESD204B/C: Architecture and Testing
Online postgraduate diploma of 800 hours in the JESD204B/C interface: architecture and test. 8 modules covering converter interfaces, JESD204B and JESD204C link layers, deterministic latency, physical layer design, FPGA implementation and link testing, with an assigned technical tutor.
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What you will be able to do
Explain the layered architecture and parameters of JESD204.
Configure JESD204B links with 8b/10b encoding.
Implement JESD204C links with 64b/66b encoding.
Achieve deterministic latency using SYSREF and subclass 1.
Design the physical layer and layout of multi-gigabit links.
Integrate JESD204 cores in FPGAs with control software.
Test and debug links using BER, patterns and margins.
Who it's for
- FPGA engineers integrating high-speed data converters.
- High-speed hardware engineers designing multi-gigabit boards.
- Converter applications engineers supporting JESD204 designs.
- Radio systems engineers working on SDR, radar or phased arrays.
- Interface validation engineers responsible for link bring-up.
- Electronic test engineers running BER and latency tests.
- Engineering or science graduates seeking to enter telecommunications.
What you'll work with
- JEDEC JESD204C (serial interface for data converters, 64b/66b)
- JEDEC JESD204B.01 (serial interface for data converters, 8b/10b)
- JEDEC JESD204A (multi-lane serial interface for data converters)
- OIF-CEI-04.0 (common electrical I/O for high-speed links)
- IEEE 1149.6-2015 (boundary scan for AC-coupled and differential networks)
- IEEE 1241-2010 (test methods for analogue-to-digital converters)
- AMD Vivado
- Intel Quartus Prime
- Analog Devices ACE
- MATLAB
8 modules
1.1Limitations of LVDS and parallel CMOS1.2Motivation for serial interfaces1.3Evolution of JESD204 through revisions A, B and C1.4Subclasses 0, 1 and 21.5Physical, link, transport and application layers1.6Parameters L, M, F, S, K and N1.7Multi-converter system topologies1.8The ADC, DAC and FPGA ecosystem1.9System clock requirements1.10Case study: JESD mode for an SDR receiver
2.1Mapping samples to octets2.28b/10b encoding and disparity2.3Code group synchronisation with SYNC~2.4Initial lane alignment sequence (ILAS)2.5Frame and multiframe alignment2.6Scrambling and its spectral effect2.7Link error monitoring2.8Control and alignment characters2.9Typical lane configurations2.10Lab: ILAS analysis on an FPGA
3.164b/66b and 64b/80b encoding3.2Blocks, multiblocks and extended multiblocks3.3Sync header stream and CRC3.4FEC error correction3.5Line rates up to 32 Gb/s3.6Implementation differences from 204B3.7Link management without SYNC~3.8Efficiency and overhead3.9Compatibility and migration3.10Practical exercise: JESD204C link in Vivado
4.1SYSREF and its timing4.2Subclass 1: deterministic latency4.3Multiframe clock and LMFC4.4Elastic buffers and RBD4.5Aligning multiple converters4.6Clock generation with jitter cleaners4.7SYSREF setup and hold requirements4.8End-to-end latency measurement4.9Beamforming and phased array applications4.10Workshop: phase alignment between two ADCs
5.1SerDes transceivers in FPGAs5.2TX and RX equalisation5.3Electrical requirements according to OIF-CEI5.4Lane routing and AC coupling5.5Eye diagrams and masks5.6Channel losses and budget5.7Transceiver power supply5.8FMC and FMC+ connectors5.9JESD schematic review5.10Lab: eye diagram with IBERT
6.1AMD and Intel JESD204 IP6.2Integration with transceivers and clocks6.3Transport layer and sample packing6.4AXI-Stream interface to processing6.5Converter configuration via SPI6.6The JESD204 framework in Linux6.7Link start-up state machines6.8Debugging with ILA and status registers6.9Reset management and start-up sequence6.10Practical exercise: ADC-FPGA link with an evaluation board
7.1PRBS patterns and BER testing7.2Transport layer testing with patterns7.3Typical synchronisation failures7.4Diagnosing disparity errors7.5Equalisation margin sweeps7.6Deterministic latency tests7.7IEEE 1149.6 boundary scan in production7.8Converter characterisation through the link7.9Test automation7.10Case study: a link that loses synchronisation
8.1Acquisition system requirements8.2Selection of mode and parameters8.3Clock and SYSREF design8.4FPGA implementation8.5Physical layer validation8.6Latency and BER testing8.7Test report8.8Integration documentation8.9Report and presentation8.10Final project: final review with your tutor
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable materials, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, making it compatible with work.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is AMD Vivado, Intel Quartus Prime, Analog Devices ACE and MATLAB, in free, academic or evaluation versions. Tests are studied on real procedures for ILAS and synchronisation analysis on FPGAs, BER testing with PRBS patterns and deterministic latency measurement. Assessment is continuous by module plus the final project.
Standards covered: JEDEC JESD204C, JEDEC JESD204B.01, JEDEC JESD204A, OIF-CEI-04.0, IEEE 1149.6-2015, IEEE 1241-2010.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- Prior technical training or professional experience in the sector. No university degree is required.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with AMD Vivado, Intel Quartus Prime, Analog Devices ACE and MATLAB, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.
Prior technical training or professional experience in the sector (no university degree required), a computer able to run the software and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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