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Postgraduate DiplomaElectronics, Embedded Systems & Telecom Applications open

Diploma in Deterministic Design and Ultra-Low Latency

Online postgraduate diploma of 800 hours in Deterministic Design and Ultra-Low Latency: 8 modules covering sources of latency and non-determinism, deterministic hardware architecture, low-latency operating systems and programming, ultra-low-latency networking, FPGA logic for critical paths, and measurement and validation, with an assigned technical tutor.

Duration6–8 months
ModeOnline
LanguageEnglish
Start datesSet by the faculty
AwardSEIUM Institute diploma
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Learning outcomes

What you will be able to do

01

Identify the sources of latency and jitter in computing systems.

02

Configure hardware platforms for deterministic behaviour.

03

Tune the operating system to minimise tail latency.

04

Programme critical paths without locks or dynamic allocation.

05

Implement low-latency networking with kernel bypass and PTP synchronisation.

06

Design FPGA logic for nanosecond-scale paths.

07

Measure and validate timing guarantees in production.

Profile

Who it's for

  • Low-latency engineers who need predictable tail latency, not just good averages.
  • Trading systems engineers working on market data and order execution paths.
  • Real-time software engineers tuning Linux and RTOS platforms.
  • Performance engineers profiling and optimising critical code paths.
  • High-frequency networking engineers working with kernel bypass and PTP.
  • Network FPGA engineers building nanosecond-scale pipelines.
  • Engineering or science graduates looking to enter the financial markets sector.
Standards & tools

What you'll work with

  • IEEE 1588-2019 – PTP (Precision Time Protocol)
  • Commission Delegated Regulation (EU) 2017/574 – RTS 25 (accuracy of business clocks)
  • IEEE 802.1AS-2020 (timing and synchronisation for time-sensitive applications)
  • IEEE 802.1Qbv-2015 (enhancements for scheduled traffic)
  • IEC 61784-2 (real-time Ethernet communication profiles)
  • IEC 61508-3:2010 (functional safety software requirements)
  • DPDK
  • Intel VTune Profiler
  • linuxptp
  • rt-tests (cyclictest)
Syllabus

8 modules

  1. 1.1Mean latency versus tail latency
  2. 1.2p99, p99.9 and worst-case percentiles
  3. 1.3Jitter and its hardware causes
  4. 1.4Interrupts, SMIs and firmware
  5. 1.5Caches, TLB and branch prediction
  6. 1.6Operating system scheduler interference
  7. 1.7Dynamic memory allocation
  8. 1.8Garbage collection in managed languages
  9. 1.9Reliable measurement and observer bias
  10. 1.10Lab: latency histogram with cyclictest
  1. 2.1CPU selection and fixed frequency
  2. 2.2Disabling C-states and P-states
  3. 2.3NUMA and memory locality
  4. 2.4Cache partitioning with Intel CAT
  5. 2.5Cache locking and TCM in embedded systems
  6. 2.6FPGAs for critical paths
  7. 2.7NICs with offload and hardware timestamping
  8. 2.8Reference clocks and oscillators
  9. 2.9PCIe interconnects and latency
  10. 2.10Practical: BIOS and x86 platform tuning
  1. 3.1PREEMPT_RT and the preemption model
  2. 3.2Isolated cores with isolcpus and nohz_full
  3. 3.3IRQ affinity and interrupt steering
  4. 3.4SCHED_FIFO and SCHED_RR priorities
  5. 3.5Memory locking with mlockall
  6. 3.6Busy-polling threads
  7. 3.7RTOS and partitioning hypervisors
  8. 3.8Kernel latency measurement
  9. 3.9tuned settings and latency profiles
  10. 3.10Lab: isolated core for a control loop
  1. 4.1Lock-free structures and SPSC queues
  2. 4.2Atomics and the C++ memory model
  3. 4.3False sharing and cache-line alignment
  4. 4.4Memory preallocation and pools
  5. 4.5Avoiding system calls on the critical path
  6. 4.6Modern C++ without exceptions or RTTI
  7. 4.7Rust for deterministic systems
  8. 4.8Predictable branching and compact data
  9. 4.9Measurement with the TSC and rdtsc
  10. 4.10Practical: lock-free producer-consumer queue
  1. 5.1Kernel bypass with DPDK
  2. 5.2AF_XDP and eBPF networking
  3. 5.3RDMA and InfiniBand
  4. 5.4User-space TCP stacks
  5. 5.5Multicast and market data feeds
  6. 5.6PTP synchronisation and timestamping
  7. 5.7Deterministic TSN networks
  8. 5.8Microwave links and direct routes
  9. 5.9Wire-latency measurement
  10. 5.10Workshop: packet forwarding with DPDK
  1. 6.1Packet processing on FPGA
  2. 6.2Nanosecond latencies and pipelines
  3. 6.3Low-latency transceivers and MACs
  4. 6.4Decision logic in hardware
  5. 6.5FPGA-CPU interfaces
  6. 6.6Deterministic pipeline verification
  7. 6.7Clocking, CDC and metastability
  8. 6.8Comparison of FPGA, SmartNIC and CPU
  9. 6.9Hardware risk controls
  10. 6.10Lab: packet parser on FPGA
  1. 7.1Capture with hardware timestamping
  2. 7.2Analysis of latency distributions
  3. 7.3Load and worst-case testing
  4. 7.4Performance regressions in CI
  5. 7.5Time traceability according to RTS 25
  6. 7.6Continuous monitoring in production
  7. 7.7Diagnosing latency spikes
  8. 7.8Determinism in industrial control
  9. 7.9Documentation of timing guarantees
  10. 7.10Case study: latency spikes in a trading system
  1. 8.1Latency and jitter requirements
  2. 8.2Hardware and software architecture
  3. 8.3Platform and operating system tuning
  4. 8.4Critical path implementation
  5. 8.5Instrumentation and measurement
  6. 8.6Tail latency analysis
  7. 8.7Timing guarantees report
  8. 8.8Improvement proposals
  9. 8.9Report and presentation
  10. 8.10Final project: final review with your tutor
Methodology, software & labs

How you'll learn

The programme is delivered 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so you can combine it with your job.

Each module combines theory, guided reading of the original standard and applied exercises. The working software is DPDK, Intel VTune Profiler, linuxptp and rt-tests (cyclictest), in free, academic or evaluation versions. Testing is studied through real procedures: tail latency measurement with hardware timestamping, platform tuning for real time and packet forwarding with kernel bypass. Assessment is continuous, module by module, plus the final project.

Standards covered: IEEE 1588-2019 (PTP), Commission Delegated Regulation (EU) 2017/574 (RTS 25), IEEE 802.1AS-2020, IEEE 802.1Qbv-2015, IEC 61784-2 and IEC 61508-3:2010.

Assigned technical tutor:every module ends with a deliverable that your tutor marks individually.
Standards-based learning:guided reading of IEEE 1588 (PTP), RTS 25 and IEEE 802.1AS applied to real cases, not as a theoretical annex.
Industry software:DPDK, Intel VTune Profiler, linuxptp and rt-tests (cyclictest), in free, academic or evaluation versions.
Final project:an ultra-low-latency system built and tuned end to end, with tail latency measured and timing guarantees documented, reviewed by your tutor.
Flexible format:100% online, no fixed timetables, compatible with full-time work.
Capstone project

Build it end to end

Your final project follows the real engineering workflow, step by step, reviewed by your tutor.

Latency requirements
Set the latency and jitter requirements of the system.
Architecture and tuning
Design the hardware and software architecture and tune the platform and OS.
Critical path implementation
Implement the critical path with lock-free, allocation-free code.
Instrumentation and tail analysis
Instrument the system, measure it and analyse the latency tail.
Final project
Deliver the timing guarantees report with improvement proposals, reviewed by your tutor.
Career opportunities

Where this takes you

Low-latency engineerTrading systems engineerReal-time software engineerPerformance engineerHigh-frequency networking engineerNetwork FPGA engineer
Admissions & scholarships

Requirements

  • Prior technical training or professional experience in the sector. No university degree is required.
  • An internet connection and a computer capable of running the programme software.
  • English sufficient to read technical standards.

Ready to start?

Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.

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FAQ

Frequently asked questions

The programme totals 800 hours over 6–8 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.

You work with DPDK, Intel VTune Profiler, linuxptp and rt-tests (cyclictest), using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.

A SEIUM Institute diploma, awarded on passing the continuous assessment and the final project. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.

Yes. Modules passed are recognised in a higher programme in the same area (postgraduate diploma or master's). Ask about the recognition policy when you enrol.

Prior technical training or professional experience in the sector (no university degree required), a computer able to run the programme software and English sufficient to read technical standards.

Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.

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