Master’s in High-Speed PCB Design
Online master's programme of 1,900 hours in high-speed PCB design (SI/PI, DDR, SerDes, stack-ups and current return). 12 modules covering high-speed signals, materials and stack-up, traces and interconnects, signal and power integrity, DDR memory, multigigabit serial interfaces, EMC, thermal and mechanical management, manufacturing and DFM, and lab validation, applied to IPC-2221B, IPC-2141A and IPC-6012 with an assigned technical tutor.
Master’s in High-Speed PCB Design — studying from Australia
Electronics and embedded systems underpin a wide range of Australian industries, including defence, mining automation, medical devices and consumer technology. The telecommunications sector is significant, with ongoing investment in fibre, mobile networks and satellite communications for remote regions. Research organisations such as CSIRO and university groups contribute to advances in sensing, communications and signal processing. Engineers typically work on hardware design, firmware development, testing and certification. Employers include telecommunications carriers, defence contractors, instrumentation companies and product manufacturers.
Fees for Australia: A$9,410 (AUD), with instalments and employer sponsorship available.
Relevant bodies in Australia
Typical roles
Questions from Australia
Is this qualification recognised for electronics engineering in Australia?
SEIUM's qualifications are private and not official state degrees, and they are not accredited by Engineers Australia or the Australian Communications and Media Authority. Recognition for electronics and telecom roles generally depends on accredited degrees, licences and experience. Employers or the relevant body make the final decision.
Which Australian employers hire embedded and telecom engineers?
Australia has telecommunications carriers, defence electronics firms, medical device makers, mining technology companies and IoT developers. Employers mostly assess your hands-on skills, project record and certifications. Ask prospective employers whether they would consider a private online qualification.
Can I study this part-time while working, and how is it supported?
The courses are 100% online and taught in English, so you can study from anywhere in Australia without needing a student visa. Specialist courses take 300 hours, diplomas 800 and master's 1,900. Each student has an assigned technical tutor, fees are payable in instalments, and employer sponsorship may be possible.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Understand the behaviour of high-speed signals.
Design stack-ups and select materials.
Route high-speed interconnects correctly.
Simulate signal and power integrity.
Design DDR and multigigabit serial interfaces.
Apply EMC, thermal and manufacturing criteria.
Validate boards in the lab and correlate results with simulation.
Who it's for
- High-speed PCB designers.
- Signal integrity engineers.
- Hardware engineers working on dense, fast boards.
- Power integrity engineers.
- Hardware validation engineers.
- Layout engineers.
- Engineering or science graduates looking to enter telecommunications.
What you'll work with
- IPC-2221B (generic standard on printed board design)
- IPC-2141A (design guide for high-speed controlled impedance circuit boards)
- IPC-6012 (qualification and performance of rigid printed boards)
- IPC-2226 (design standard for HDI printed boards)
- JEDEC JESD79-4 (DDR4 SDRAM standard)
- PCI Express Base Specification 5.0 (PCIe interface)
- IEEE 802.3 (Ethernet)
- Altium Designer
- Cadence Allegro
- Siemens HyperLynx
- Ansys SIwave
- Keysight ADS
12 modules
1.1Rise time and bandwidth1.2When a trace becomes a transmission line1.3Characteristic impedance1.4Reflections and terminations1.5Crosstalk1.6Conductor and dielectric losses1.7Differential signalling1.8DDR, PCIe, USB and Ethernet interfaces1.9Timing budget1.10Case study: analysis of a PCIe Gen4 link
2.1FR-4 and low-loss materials2.2Dielectric constant and loss tangent2.3Fibre weave effect2.4Copper roughness2.5Stack-up design2.6Impedance control2.7Fabricators and tolerances2.8Material costs2.9Communicating with the fabricator2.10Lab: design of a 10-layer stack-up
3.1Microstrip and stripline3.2Differential pairs3.3Length matching3.4Serpentines and their effect3.5Vias and stubs3.6Back-drilling3.7Blind and buried vias3.8Layer transitions3.9High-speed connectors3.10Practical exercise: routing differential pairs
4.1Eye diagrams4.2Jitter and its components4.3Inter-symbol interference4.4CTLE and DFE equalisation4.5Pre-emphasis4.6IBIS and IBIS-AMI models4.7Channel S-parameters4.8Channel simulation4.9Mask compliance4.10Lab: channel simulation with HyperLynx
5.1Power distribution network5.2Target impedance5.3Decoupling by frequency band5.4Planes and resonances5.5Simultaneous switching noise5.6DC voltage drop5.7SI/PI co-simulation5.8PDN measurement5.9Decoupling optimisation5.10Practical exercise: PDN analysis of an FPGA
6.1DDR4 and DDR5 architecture6.2Fly-by topology6.3ODT terminations6.4Timing constraints6.5Byte lane matching6.6Write levelling6.7LPDDR6.8DDR simulation6.9Interface validation6.10Lab: layout of a DDR4 interface
7.1PCIe Gen4 and Gen57.2USB 3.x and USB47.3Ethernet from 10G to 100G7.4FPGA SerDes7.5Channels and insertion loss7.6Retimers and redrivers7.7Connectors and cables7.8Compliance testing7.9Vendor design rules7.10Practical exercise: loss budget for a 25 Gbps channel
8.1Radiation from differential pairs8.2Return paths and plane gaps8.3Via stitching8.4On-board shielding8.5Clock filtering8.6Spread spectrum8.7EMC layout rules8.8Emissions simulation8.9Troubleshooting8.10Lab: emissions measurement of a board
9.1Heat dissipation in high-power components9.2Thermal vias9.3Heatsinks and ventilation9.4Thermal simulation9.5PCB warpage9.6BGAs and solder joint reliability9.7Stiffeners9.8Assembly and testing9.9Thermal cycling9.10Practical exercise: thermal simulation of an FPGA board
10.1Manufacturing rules10.2Minimum widths and clearances10.3Microvias and HDI10.4Surface finishes10.5Panels and fiducials10.6SMT assembly10.7Electrical testing10.8AOI and X-ray inspection10.9Manufacturing documentation10.10Workshop: DFM review of an HDI design
11.1Impedance measurement with TDR11.2VNA measurements11.3High-speed oscilloscopes11.4Jitter analysis11.5Compliance testing11.6Fixtures and de-embedding11.7Simulation–measurement correlation11.8Fault debugging11.9Validation reports11.10Practical exercise: TDR measurement of a trace
12.1Board requirements12.2Stack-up and materials12.3Floorplanning12.4High-speed routing12.5SI and PI simulations12.6DFM and EMC review12.7Prototype validation12.8Analysis of results12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within each intake, so it fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Altium Designer, Cadence Allegro, Siemens HyperLynx, Ansys SIwave and Keysight ADS, in free, academic or evaluation versions. Testing is studied through real procedures for TDR impedance measurements, eye diagram analysis and interface compliance tests. Assessment is continuous by module, plus the final Master's Thesis.
Standards covered: IPC-2221B, IPC-2141A, IPC-6012, IPC-2226, JEDEC JESD79-4, PCI Express Base Specification 5.0, IEEE 802.3.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer able to run the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Altium Designer, Cadence Allegro, Siemens HyperLynx, Ansys SIwave and Keysight ADS, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the software, and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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