Master’s in High-Speed PCB Design Engineering
Online master's programme of 1,900 hours in high-speed PCB design engineering. 12 modules covering transmission lines, materials and stack-ups, vias, crosstalk, DDR memory interfaces, multigigabit serial links, power integrity, board-level EMC and lab validation to IPC-2141A, IPC-2221B and IPC-2226, with an assigned technical tutor.
Master’s in High-Speed PCB Design Engineering — studying from Australia
Electronics and embedded systems underpin a wide range of Australian industries, including defence, mining automation, medical devices and consumer technology. The telecommunications sector is significant, with ongoing investment in fibre, mobile networks and satellite communications for remote regions. Research organisations such as CSIRO and university groups contribute to advances in sensing, communications and signal processing. Engineers typically work on hardware design, firmware development, testing and certification. Employers include telecommunications carriers, defence contractors, instrumentation companies and product manufacturers.
Fees for Australia: A$14,200 (AUD), with instalments and employer sponsorship available.
Relevant bodies in Australia
Typical roles
Questions from Australia
Is this qualification recognised for electronics engineering in Australia?
SEIUM's qualifications are private and not official state degrees, and they are not accredited by Engineers Australia or the Australian Communications and Media Authority. Recognition for electronics and telecom roles generally depends on accredited degrees, licences and experience. Employers or the relevant body make the final decision.
Which Australian employers hire embedded and telecom engineers?
Australia has telecommunications carriers, defence electronics firms, medical device makers, mining technology companies and IoT developers. Employers mostly assess your hands-on skills, project record and certifications. Ask prospective employers whether they would consider a private online qualification.
Can I study this part-time while working, and how is it supported?
The courses are 100% online and taught in English, so you can study from anywhere in Australia without needing a student visa. Specialist courses take 300 hours, diplomas 800 and master's 1,900. Each student has an assigned technical tutor, fees are payable in instalments, and employer sponsorship may be possible.
Take the controls.
Run a real engineering trade-off from this field. Move the sliders, watch the model react in real time and beat the challenge.
What you will be able to do
Design layer stack-ups and controlled-impedance structures.
Apply transmission line theory to the routing of fast signals.
Design high-speed DDR, PCIe and Ethernet interfaces.
Simulate channels with IBIS models and S-parameters.
Control crosstalk, losses and via discontinuities.
Ensure power integrity in fast digital systems.
Validate designs through laboratory measurements.
Who it's for
- High-speed PCB designers working on dense multilayer boards.
- Signal integrity engineers simulating DDR and SerDes channels.
- Digital hardware engineers designing processor and FPGA boards.
- Interface validation engineers carrying out compliance testing.
- Power integrity engineers responsible for PDN design.
- Interconnect engineers working on connectors, cables and backplanes.
- Engineering or science graduates seeking to move into telecommunications.
What you'll work with
- IPC-2141A (design guide for controlled-impedance printed circuits)
- IPC-2221B (generic standard on printed board design)
- IPC-2226 (design of high-density interconnect boards)
- IPC-4101 (base materials for rigid boards)
- PCI Express Base Specification 5.0 (high-speed serial interconnect)
- IEEE 802.3 (Ethernet)
- JEDEC JESD79-5 (DDR5 SDRAM)
- IBIS 7.0 (I/O Buffer Information Specification)
- Cadence Allegro
- Altium Designer
- Ansys SIwave
- Keysight ADS
- HyperLynx
12 modules · 1900 h
1.1Rise times and spectral content1.2When a track becomes a transmission line1.3Trends in interface speeds1.4Timing and noise budgets1.5Failure modes of fast signals1.6Return current and reference planes1.7Simulation-driven design flow1.8Collaboration with the board manufacturer1.9Cost versus performance1.10Case study: analysis of a signal integrity failure
2.1Characteristic impedance and propagation2.2Microstrip and stripline2.3Coupled differential pairs2.4Reflections and bounce diagrams2.5Series, parallel and Thevenin terminations2.6Conductor and dielectric losses2.7Copper roughness and skin effect2.8Dispersion and group delay2.9Field-solver impedance calculators2.10Practical: impedance calculation with a field solver
3.1FR-4 and low-loss laminates3.2Dielectric constant and dissipation factor3.3Glass-weave effect3.4Designing symmetrical stack-ups3.5Manufacturing impedance tolerances3.6HDI boards and microvias3.7Blind, buried and stacked vias3.8Cost of materials and processes3.9Stack-up specification for the manufacturer3.10Workshop: twelve-layer stack-up for a processor
4.1Electrical model of a via4.2Via stubs and back-drilling4.3Return vias at layer transitions4.4Antipads and their optimisation4.5Connectors and transitions4.6Series AC coupling capacitors4.7BGA component footprints4.8Breakout routing for fine-pitch BGAs4.93D simulation of discontinuities4.10Lab: optimisation of a via transition
5.1Capacitive and inductive coupling5.2Near-end and far-end crosstalk5.3Track spacing rules5.4Voids and splits in planes5.5Reference plane changes5.6Simultaneous switching noise5.7Skew in differential pairs5.8Differential-to-common-mode conversion5.9Serpentine routing and its effect5.10Practical: crosstalk simulation in HyperLynx
6.1DDR4 and DDR5 architecture6.2Fly-by and point-to-point topologies6.3Length matching and byte lanes6.4On-die termination (ODT)6.5Read and write training6.6DDR timing budget6.7LPDDR interfaces in mobile devices6.8Simulation with IBIS models6.9Manufacturer routing rules6.10Workshop: routing a DDR4 interface
7.1SerDes architecture and encoding7.2PCI Express generations 4 to 67.3Ethernet from 25 to 100 Gb/s7.4USB 3 and Thunderbolt7.5Insertion and return loss7.6CTLE and DFE equalisation7.7Simulation with IBIS-AMI models7.8Statistical channel analysis7.9PAM4 signalling7.10Lab: PCIe channel simulation in ADS
8.1Power distribution network8.2Target impedance calculation8.3Decoupling capacitors and resonances8.4Inter-plane capacitance8.5DC voltage drop8.6Rail noise in processors8.7Simulation with SIwave8.8Measuring network impedance8.9Interaction with regulators8.10Practical: design of an FPGA decoupling network
9.1Emission sources in fast boards9.2Current loops and unintentional antennas9.3Shielding and board edges9.4Filtering external interfaces9.5Spread-spectrum clocking9.6Plane stitching with vias9.7Grounding design in mixed-signal systems9.8EMC design rules9.9Pre-compliance testing9.10Case study: reducing a board's emissions
10.1Time-domain reflectometry10.2Vector network analyser10.3S-parameter extraction10.4Fixture de-embedding10.5Eye diagrams and jitter10.6High-speed probes10.7Interface compliance testing10.8Correlation between simulation and measurement10.9Impedance test coupons10.10Lab: TDR measurement of an impedance coupon
11.1Electrical constraint management in Allegro11.2Net classes and impedance rules11.3Length and delay constraints11.4Interactive differential pair routing11.5Routing channel planning11.6Checklist-based design review11.7Collaboration with signal integrity11.8Manufacturing documentation for high speed11.9Control of late changes11.10Workshop: defining constraints for a server board
12.1Definition of the board under study12.2Stack-up design12.3Design of high-speed interfaces12.4Signal integrity simulation12.5Power network design12.6EMC design review12.7Validation plan12.8Conclusions and future work12.9Master's Thesis report12.10Master's Thesis: defence before a panel
How you'll learn
Training is 100% online on the SEIUM campus, with downloadable material, recorded classes and an assigned technical tutor. There are no fixed timetables: you progress at your own pace within the intake, so it fits around your job.
Each module combines theory, guided reading of the original standard and applied exercises. The working software is Cadence Allegro, Altium Designer, Ansys SIwave, Keysight ADS and HyperLynx, in free, academic or evaluation versions. Work is based on real procedures: designing controlled-impedance stack-ups, simulating high-speed serial channels and taking measurements with reflectometry and a network analyser. Assessment is continuous per module, plus the final Master's Thesis.
Standards covered: IPC-2141A, IPC-2221B, IPC-2226, IPC-4101, PCI Express Base Specification 5.0, IEEE 802.3, JEDEC JESD79-5, IBIS 7.0.
Build it end to end
Your final project follows the real engineering workflow, step by step, reviewed by your tutor.
Where this takes you
Requirements
- University degree in engineering, science or architecture, or equivalent demonstrable professional experience.
- Internet connection and a computer capable of running the programme software.
- English sufficient to read technical standards.
Ready to start?
Send your application today. Our admissions team replies within 72 hours with your study plan and funding options.
Frequently asked questions
The programme totals 1,900 hours over 12–14 months. You set your own pace within each intake, and your tutor helps you plan the workload around your job.
You work with Cadence Allegro, Altium Designer, Ansys SIwave, Keysight ADS and HyperLynx, using free, academic or evaluation versions. Your tutor indicates the free alternative wherever one exists.
A SEIUM Institute diploma, awarded on passing the continuous assessment and the Master's Thesis. It is SEIUM's own qualification, not an official state degree; its recognition depends on the programme completed and the regulations of each country.
Yes. Modules passed in a course or postgraduate diploma in the same area are recognised in the higher programme. Ask about the recognition policy when you enrol.
A university degree in engineering, science or architecture (or equivalent professional experience), a computer able to run the programme software, and English sufficient to read technical standards.
Start dates are set by SEIUM's faculty for each intake. Our admissions team will confirm the next available date when you apply.
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